Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	827232975	75845	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827232975	75845	0	0
T1	889735	131	0	0
T2	300950	79	0	0
T3	0	50	0	0
T9	0	517	0	0
T10	0	170	0	0
T11	0	652	0	0
T12	0	908	0	0
T13	0	1618	0	0
T14	0	398	0	0
T15	0	565	0	0
T16	7010	0	0	0
T17	10470	0	0	0
T18	16290	0	0	0
T19	6075	0	0	0
T20	7830	0	0	0
T21	8300	0	0	0
T22	13290	0	0	0
T23	10330	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165446595	11159	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	11159	0	0
T1	177947	21	0	0
T2	60190	15	0	0
T3	0	8	0	0
T9	0	69	0	0
T10	0	22	0	0
T11	0	97	0	0
T12	0	147	0	0
T13	0	232	0	0
T14	0	64	0	0
T15	0	108	0	0
T16	1402	0	0	0
T17	2094	0	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	2658	0	0	0
T23	2066	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165446595	10931	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	10931	0	0
T1	177947	21	0	0
T2	60190	15	0	0
T3	0	8	0	0
T9	0	68	0	0
T10	0	22	0	0
T11	0	94	0	0
T12	0	141	0	0
T13	0	225	0	0
T14	0	63	0	0
T15	0	108	0	0
T16	1402	0	0	0
T17	2094	0	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	2658	0	0	0
T23	2066	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165446595	15270	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	15270	0	0
T1	177947	27	0	0
T2	60190	16	0	0
T3	0	10	0	0
T9	0	105	0	0
T10	0	34	0	0
T11	0	131	0	0
T12	0	182	0	0
T13	0	363	0	0
T14	0	81	0	0
T15	0	108	0	0
T16	1402	0	0	0
T17	2094	0	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	2658	0	0	0
T23	2066	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165446595	15223	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	15223	0	0
T1	177947	26	0	0
T2	60190	15	0	0
T3	0	10	0	0
T9	0	105	0	0
T10	0	34	0	0
T11	0	132	0	0
T12	0	185	0	0
T13	0	315	0	0
T14	0	79	0	0
T15	0	108	0	0
T16	1402	0	0	0
T17	2094	0	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	2658	0	0	0
T23	2066	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165446595	23262	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	23262	0	0
T1	177947	36	0	0
T2	60190	18	0	0
T3	0	14	0	0
T9	0	170	0	0
T10	0	58	0	0
T11	0	198	0	0
T12	0	253	0	0
T13	0	483	0	0
T14	0	111	0	0
T15	0	133	0	0
T16	1402	0	0	0
T17	2094	0	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	2658	0	0	0
T23	2066	0	0	0