Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_io_step_down_req_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_io_div2_div_scanmode_sync	100.00	100.00					100.00
tb.dut.u_io_div4_div_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_io_ack_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_clkmgr_byp.u_all_ack_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_main_root_ctrl.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_io_root_ctrl.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_io_div2_root_ctrl.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_io_div4_root_ctrl.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_usb_root_ctrl.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_io_meas.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_io_div2_meas.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_io_div4_meas.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_main_meas.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_usb_meas.u_calib_rdy_sync	100.00	100.00					100.00
tb.dut.u_clk_io_div4_peri_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_io_div2_peri_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_io_peri_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_usb_peri_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_main_aes_trans.u_idle_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_clk_main_aes_trans.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_main_hmac_trans.u_idle_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_clk_main_hmac_trans.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_main_kmac_trans.u_idle_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_clk_main_kmac_trans.u_scanmode_sync	100.00	100.00					100.00
tb.dut.u_clk_main_otbn_trans.u_idle_sync	100.00	100.00	100.00			100.00	100.00
tb.dut.u_clk_main_otbn_trans.u_scanmode_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_io_step_down_req_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div2_div_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_io_div4_div_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_main_root_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_root_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div2_root_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div4_root_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_usb_root_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[5].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_meas.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div2_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_io_div4_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_main_meas.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_main_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33			100.00		u_usb_meas

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_io_peri_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_usb_peri_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_aes_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_aes_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_hmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_hmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_kmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_kmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_otbn_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	100.00	100.00
gen_flops.gen_stable_chks.u_mubi_xor	100.00	100.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	100.00	100.00				100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_otbn_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_step_down_req_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_io_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_all_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div4_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div2_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_usb_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	6	6

---

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Cond Coverage for Module : prim_mubi4_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

Branch Coverage for Module : prim_mubi4_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	22540	22540	0	0
OutputsKnown_A	2147483647	2147483647	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	992679570	977195298	0	14490
gen_flops.gen_stable_chks.OutputDelay_A	2147483647	2147483647	0	16905
gen_flops.gen_stable_chks.OutputIfUnstable_A	2147483647	190766	0	0
gen_no_flops.OutputDelay_A	2147483647	2147483647	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	22540	22540	0	0
T1	28	28	0	0
T2	28	28	0	0
T4	28	28	0	0
T5	28	28	0	0
T6	28	28	0	0
T16	28	28	0	0
T17	28	28	0	0
T18	28	28	0	0
T19	28	28	0	0
T20	28	28	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	12205920	12204635	0	0
T2	7836321	7825183	0	0
T4	76296	70689	0	0
T5	53998	49797	0	0
T6	124182	122156	0	0
T16	87961	84810	0	0
T17	135033	131959	0	0
T18	85043	79651	0	0
T19	76231	72791	0	0
T20	40872	38915	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	992679570	977195298	0	14490
T1	1067682	1067544	0	18
T2	361140	360474	0	18
T4	17208	15810	0	18
T5	12138	11064	0	18
T6	9504	9294	0	18
T16	8412	8058	0	18
T17	12564	12228	0	18
T18	19548	18174	0	18
T19	7290	6924	0	18
T20	9396	8904	0	18

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	16905
T1	4331724	4331192	0	21
T2	2988716	2983552	0	21
T4	20556	18885	0	21
T5	14501	13220	0	21
T6	44534	43611	0	21
T16	30634	29380	0	21
T17	47489	46241	0	21
T18	22677	21083	0	21
T19	26695	25293	0	21
T20	10903	10308	0	21

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	190766	0	0
T1	4331724	1469	0	0
T2	2988716	862	0	0
T4	11952	213	0	0
T5	14501	113	0	0
T6	44534	166	0	0
T16	30634	103	0	0
T17	47489	16	0	0
T18	22677	166	0	0
T19	26695	40	0	0
T20	10903	40	0	0
T21	4867	0	0	0
T22	0	162	0	0
T23	0	87	0	0
T36	0	12	0	0
T65	0	25	0	0
T97	0	68	0	0
T98	0	39	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	6806514	6805878	0	0
T2	4486465	4480962	0	0
T4	38532	35955	0	0
T5	27359	25474	0	0
T6	70144	69212	0	0
T16	48915	47333	0	0
T17	74980	73451	0	0
T18	42818	40355	0	0
T19	42246	40535	0	0
T20	20573	19664	0	0

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

---

Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	438700817	434222822	0	0
gen_flops.gen_stable_chks.OutputDelay_A	438700817	434215603	0	2415
gen_flops.gen_stable_chks.OutputIfUnstable_A	438700817	26094	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438700817	434222822	0	0
T1	764386	764293	0	0
T2	508696	507753	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	8006	7844	0	0
T16	5386	5169	0	0
T17	8381	8164	0	0
T18	3129	2912	0	0
T19	4737	4492	0	0
T20	1467	1387	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438700817	434215603	0	2415
T1	764386	764292	0	3
T2	508696	507738	0	3
T4	2868	2635	0	3
T5	2023	1844	0	3
T6	8006	7841	0	3
T16	5386	5166	0	3
T17	8381	8161	0	3
T18	3129	2909	0	3
T19	4737	4489	0	3
T20	1467	1384	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438700817	26094	0	0
T1	764386	135	0	0
T2	508696	114	0	0
T5	2023	30	0	0
T6	8006	30	0	0
T16	5386	30	0	0
T17	8381	0	0	0
T18	3129	0	0	0
T19	4737	0	0	0
T20	1467	0	0	0
T21	1547	0	0	0
T22	0	51	0	0
T23	0	38	0	0
T65	0	13	0	0
T97	0	17	0	0
T98	0	17	0	0

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	165446595	162873343	0	0
gen_no_flops.OutputDelay_A	165446595	162873343	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	165446595	162873343	0	0
gen_no_flops.OutputDelay_A	165446595	162873343	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

---

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	165446595	162873343	0	0
gen_flops.gen_stable_chks.OutputDelay_A	165446595	162865883	0	2415
gen_flops.gen_stable_chks.OutputIfUnstable_A	165446595	16101	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162865883	0	2415
T1	177947	177924	0	3
T2	60190	60079	0	3
T4	2868	2635	0	3
T5	2023	1844	0	3
T6	1584	1549	0	3
T16	1402	1343	0	3
T17	2094	2038	0	3
T18	3258	3029	0	3
T19	1215	1154	0	3
T20	1566	1484	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	16101	0	0
T1	177947	109	0	0
T2	60190	78	0	0
T5	2023	19	0	0
T6	1584	23	0	0
T16	1402	17	0	0
T17	2094	0	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	0	67	0	0
T23	0	14	0	0
T36	0	12	0	0
T97	0	31	0	0
T98	0	12	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T1

---

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T1
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	165446595	162873343	0	0
gen_flops.gen_stable_chks.OutputDelay_A	165446595	162865883	0	2415
gen_flops.gen_stable_chks.OutputIfUnstable_A	165446595	18384	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162865883	0	2415
T1	177947	177924	0	3
T2	60190	60079	0	3
T4	2868	2635	0	3
T5	2023	1844	0	3
T6	1584	1549	0	3
T16	1402	1343	0	3
T17	2094	2038	0	3
T18	3258	3029	0	3
T19	1215	1154	0	3
T20	1566	1484	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	18384	0	0
T1	177947	100	0	0
T2	60190	98	0	0
T5	2023	24	0	0
T6	1584	51	0	0
T16	1402	20	0	0
T17	2094	0	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	0	44	0	0
T23	0	35	0	0
T65	0	12	0	0
T97	0	20	0	0
T98	0	10	0	0

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	468092615	465662491	0	0
gen_no_flops.OutputDelay_A	468092615	465662491	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	465662491	0	0
T1	802861	802811	0	0
T2	589910	589500	0	0
T4	2988	2891	0	0
T5	2108	2068	0	0
T6	8340	8313	0	0
T16	5611	5471	0	0
T17	8730	8604	0	0
T18	3258	3175	0	0
T19	4882	4741	0	0
T20	1576	1535	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	465662491	0	0
T1	802861	802811	0	0
T2	589910	589500	0	0
T4	2988	2891	0	0
T5	2108	2068	0	0
T6	8340	8313	0	0
T16	5611	5471	0	0
T17	8730	8604	0	0
T18	3258	3175	0	0
T19	4882	4741	0	0
T20	1576	1535	0	0

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	438700817	436398762	0	0
gen_no_flops.OutputDelay_A	438700817	436398762	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438700817	436398762	0	0
T1	764386	764338	0	0
T2	508696	508301	0	0
T4	2868	2775	0	0
T5	2023	1985	0	0
T6	8006	7981	0	0
T16	5386	5251	0	0
T17	8381	8260	0	0
T18	3129	3049	0	0
T19	4737	4602	0	0
T20	1467	1428	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438700817	436398762	0	0
T1	764386	764338	0	0
T2	508696	508301	0	0
T4	2868	2775	0	0
T5	2023	1985	0	0
T6	8006	7981	0	0
T16	5386	5251	0	0
T17	8381	8260	0	0
T18	3129	3049	0	0
T19	4737	4602	0	0
T20	1467	1428	0	0

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	218453085	218453085	0	0
gen_no_flops.OutputDelay_A	218453085	218453085	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218453085	218453085	0	0
T1	382407	382407	0	0
T2	257866	257866	0	0
T4	1388	1388	0	0
T5	1098	1098	0	0
T6	4621	4621	0	0
T16	2913	2913	0	0
T17	4130	4130	0	0
T18	1525	1525	0	0
T19	2301	2301	0	0
T20	714	714	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218453085	218453085	0	0
T1	382407	382407	0	0
T2	257866	257866	0	0
T4	1388	1388	0	0
T5	1098	1098	0	0
T6	4621	4621	0	0
T16	2913	2913	0	0
T17	4130	4130	0	0
T18	1525	1525	0	0
T19	2301	2301	0	0
T20	714	714	0	0

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	109225953	109225953	0	0
gen_no_flops.OutputDelay_A	109225953	109225953	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109225953	109225953	0	0
T1	191203	191203	0	0
T2	128932	128932	0	0
T4	694	694	0	0
T5	548	548	0	0
T6	2310	2310	0	0
T16	1456	1456	0	0
T17	2065	2065	0	0
T18	762	762	0	0
T19	1151	1151	0	0
T20	357	357	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109225953	109225953	0	0
T1	191203	191203	0	0
T2	128932	128932	0	0
T4	694	694	0	0
T5	548	548	0	0
T6	2310	2310	0	0
T16	1456	1456	0	0
T17	2065	2065	0	0
T18	762	762	0	0
T19	1151	1151	0	0
T20	357	357	0	0

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	224770963	223604017	0	0
gen_no_flops.OutputDelay_A	224770963	223604017	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224770963	223604017	0	0
T1	386531	386507	0	0
T2	280281	280083	0	0
T4	1434	1387	0	0
T5	1012	993	0	0
T6	4003	3991	0	0
T16	2693	2626	0	0
T17	4190	4130	0	0
T18	1564	1524	0	0
T19	2357	2290	0	0
T20	759	740	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224770963	223604017	0	0
T1	386531	386507	0	0
T2	280281	280083	0	0
T4	1434	1387	0	0
T5	1012	993	0	0
T6	4003	3991	0	0
T16	2693	2626	0	0
T17	4190	4130	0	0
T18	1564	1524	0	0
T19	2357	2290	0	0
T20	759	740	0	0

Line Coverage for Instance : tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	6	6

---

Assert Coverage for Instance : tb.dut.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	165446595	162873343	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	165446595	162865883	0	2415

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162865883	0	2415
T1	177947	177924	0	3
T2	60190	60079	0	3
T4	2868	2635	0	3
T5	2023	1844	0	3
T6	1584	1549	0	3
T16	1402	1343	0	3
T17	2094	2038	0	3
T18	3258	3029	0	3
T19	1215	1154	0	3
T20	1566	1484	0	3

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	165446595	162873343	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	165446595	162865883	0	2415

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162865883	0	2415
T1	177947	177924	0	3
T2	60190	60079	0	3
T4	2868	2635	0	3
T5	2023	1844	0	3
T6	1584	1549	0	3
T16	1402	1343	0	3
T17	2094	2038	0	3
T18	3258	3029	0	3
T19	1215	1154	0	3
T20	1566	1484	0	3

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	165446595	162873343	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	165446595	162865883	0	2415

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162865883	0	2415
T1	177947	177924	0	3
T2	60190	60079	0	3
T4	2868	2635	0	3
T5	2023	1844	0	3
T6	1584	1549	0	3
T16	1402	1343	0	3
T17	2094	2038	0	3
T18	3258	3029	0	3
T19	1215	1154	0	3
T20	1566	1484	0	3

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	165446595	162873343	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	165446595	162865883	0	2415

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162865883	0	2415
T1	177947	177924	0	3
T2	60190	60079	0	3
T4	2868	2635	0	3
T5	2023	1844	0	3
T6	1584	1549	0	3
T16	1402	1343	0	3
T17	2094	2038	0	3
T18	3258	3029	0	3
T19	1215	1154	0	3
T20	1566	1484	0	3

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	165446595	162873343	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	165446595	162865883	0	2415

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162865883	0	2415
T1	177947	177924	0	3
T2	60190	60079	0	3
T4	2868	2635	0	3
T5	2023	1844	0	3
T6	1584	1549	0	3
T16	1402	1343	0	3
T17	2094	2038	0	3
T18	3258	3029	0	3
T19	1215	1154	0	3
T20	1566	1484	0	3

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
124	1	1
128	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	165446595	162873343	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	165446595	162865883	0	2415

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162865883	0	2415
T1	177947	177924	0	3
T2	60190	60079	0	3
T4	2868	2635	0	3
T5	2023	1844	0	3
T6	1584	1549	0	3
T16	1402	1343	0	3
T17	2094	2038	0	3
T18	3258	3029	0	3
T19	1215	1154	0	3
T20	1566	1484	0	3

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	165446595	162873343	0	0
gen_no_flops.OutputDelay_A	165446595	162873343	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	165446595	162873343	0	0
gen_no_flops.OutputDelay_A	165446595	162873343	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	165446595	162873343	0	0
gen_no_flops.OutputDelay_A	165446595	162873343	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	165446595	162873343	0	0
gen_no_flops.OutputDelay_A	165446595	162873343	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162873343	0	0
T1	177947	177926	0	0
T2	60190	60094	0	0
T4	2868	2638	0	0
T5	2023	1847	0	0
T6	1584	1552	0	0
T16	1402	1346	0	0
T17	2094	2041	0	0
T18	3258	3032	0	0
T19	1215	1157	0	0
T20	1566	1487	0	0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	468092615	463372531	0	0
gen_flops.gen_stable_chks.OutputDelay_A	468092615	463365249	0	2415
gen_flops.gen_stable_chks.OutputIfUnstable_A	468092615	32635	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463372531	0	0
T1	802861	802764	0	0
T2	589910	588929	0	0
T4	2988	2748	0	0
T5	2108	1925	0	0
T6	8340	8171	0	0
T16	5611	5385	0	0
T17	8730	8504	0	0
T18	3258	3032	0	0
T19	4882	4627	0	0
T20	1576	1492	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463365249	0	2415
T1	802861	802763	0	3
T2	589910	588914	0	3
T4	2988	2745	0	3
T5	2108	1922	0	3
T6	8340	8168	0	3
T16	5611	5382	0	3
T17	8730	8501	0	3
T18	3258	3029	0	3
T19	4882	4624	0	3
T20	1576	1489	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	32635	0	0
T1	802861	285	0	0
T2	589910	135	0	0
T4	2988	56	0	0
T5	2108	8	0	0
T6	8340	17	0	0
T16	5611	10	0	0
T17	8730	4	0	0
T18	3258	45	0	0
T19	4882	8	0	0
T20	1576	9	0	0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	468092615	463372531	0	0
gen_no_flops.OutputDelay_A	468092615	463372531	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463372531	0	0
T1	802861	802764	0	0
T2	589910	588929	0	0
T4	2988	2748	0	0
T5	2108	1925	0	0
T6	8340	8171	0	0
T16	5611	5385	0	0
T17	8730	8504	0	0
T18	3258	3032	0	0
T19	4882	4627	0	0
T20	1576	1492	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463372531	0	0
T1	802861	802764	0	0
T2	589910	588929	0	0
T4	2988	2748	0	0
T5	2108	1925	0	0
T6	8340	8171	0	0
T16	5611	5385	0	0
T17	8730	8504	0	0
T18	3258	3032	0	0
T19	4882	4627	0	0
T20	1576	1492	0	0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	468092615	463372531	0	0
gen_flops.gen_stable_chks.OutputDelay_A	468092615	463365249	0	2415
gen_flops.gen_stable_chks.OutputIfUnstable_A	468092615	32699	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463372531	0	0
T1	802861	802764	0	0
T2	589910	588929	0	0
T4	2988	2748	0	0
T5	2108	1925	0	0
T6	8340	8171	0	0
T16	5611	5385	0	0
T17	8730	8504	0	0
T18	3258	3032	0	0
T19	4882	4627	0	0
T20	1576	1492	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463365249	0	2415
T1	802861	802763	0	3
T2	589910	588914	0	3
T4	2988	2745	0	3
T5	2108	1922	0	3
T6	8340	8168	0	3
T16	5611	5382	0	3
T17	8730	8501	0	3
T18	3258	3029	0	3
T19	4882	4624	0	3
T20	1576	1489	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	32699	0	0
T1	802861	274	0	0
T2	589910	161	0	0
T4	2988	55	0	0
T5	2108	12	0	0
T6	8340	15	0	0
T16	5611	10	0	0
T17	8730	4	0	0
T18	3258	45	0	0
T19	4882	12	0	0
T20	1576	13	0	0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	468092615	463372531	0	0
gen_no_flops.OutputDelay_A	468092615	463372531	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463372531	0	0
T1	802861	802764	0	0
T2	589910	588929	0	0
T4	2988	2748	0	0
T5	2108	1925	0	0
T6	8340	8171	0	0
T16	5611	5385	0	0
T17	8730	8504	0	0
T18	3258	3032	0	0
T19	4882	4627	0	0
T20	1576	1492	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463372531	0	0
T1	802861	802764	0	0
T2	589910	588929	0	0
T4	2988	2748	0	0
T5	2108	1925	0	0
T6	8340	8171	0	0
T16	5611	5385	0	0
T17	8730	8504	0	0
T18	3258	3032	0	0
T19	4882	4627	0	0
T20	1576	1492	0	0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	468092615	463372531	0	0
gen_flops.gen_stable_chks.OutputDelay_A	468092615	463365249	0	2415
gen_flops.gen_stable_chks.OutputIfUnstable_A	468092615	32478	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463372531	0	0
T1	802861	802764	0	0
T2	589910	588929	0	0
T4	2988	2748	0	0
T5	2108	1925	0	0
T6	8340	8171	0	0
T16	5611	5385	0	0
T17	8730	8504	0	0
T18	3258	3032	0	0
T19	4882	4627	0	0
T20	1576	1492	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463365249	0	2415
T1	802861	802763	0	3
T2	589910	588914	0	3
T4	2988	2745	0	3
T5	2108	1922	0	3
T6	8340	8168	0	3
T16	5611	5382	0	3
T17	8730	8501	0	3
T18	3258	3029	0	3
T19	4882	4624	0	3
T20	1576	1489	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	32478	0	0
T1	802861	301	0	0
T2	589910	131	0	0
T4	2988	53	0	0
T5	2108	12	0	0
T6	8340	15	0	0
T16	5611	6	0	0
T17	8730	4	0	0
T18	3258	29	0	0
T19	4882	8	0	0
T20	1576	9	0	0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	468092615	463372531	0	0
gen_no_flops.OutputDelay_A	468092615	463372531	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463372531	0	0
T1	802861	802764	0	0
T2	589910	588929	0	0
T4	2988	2748	0	0
T5	2108	1925	0	0
T6	8340	8171	0	0
T16	5611	5385	0	0
T17	8730	8504	0	0
T18	3258	3032	0	0
T19	4882	4627	0	0
T20	1576	1492	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463372531	0	0
T1	802861	802764	0	0
T2	589910	588929	0	0
T4	2988	2748	0	0
T5	2108	1925	0	0
T6	8340	8171	0	0
T16	5611	5385	0	0
T17	8730	8504	0	0
T18	3258	3032	0	0
T19	4882	4627	0	0
T20	1576	1492	0	0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	4	4
117	1	1
168	1	1

---

Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	468092615	463372531	0	0
gen_flops.gen_stable_chks.OutputDelay_A	468092615	463365249	0	2415
gen_flops.gen_stable_chks.OutputIfUnstable_A	468092615	32375	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463372531	0	0
T1	802861	802764	0	0
T2	589910	588929	0	0
T4	2988	2748	0	0
T5	2108	1925	0	0
T6	8340	8171	0	0
T16	5611	5385	0	0
T17	8730	8504	0	0
T18	3258	3032	0	0
T19	4882	4627	0	0
T20	1576	1492	0	0

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463365249	0	2415
T1	802861	802763	0	3
T2	589910	588914	0	3
T4	2988	2745	0	3
T5	2108	1922	0	3
T6	8340	8168	0	3
T16	5611	5382	0	3
T17	8730	8501	0	3
T18	3258	3029	0	3
T19	4882	4624	0	3
T20	1576	1489	0	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	32375	0	0
T1	802861	265	0	0
T2	589910	145	0	0
T4	2988	49	0	0
T5	2108	8	0	0
T6	8340	15	0	0
T16	5611	10	0	0
T17	8730	4	0	0
T18	3258	47	0	0
T19	4882	12	0	0
T20	1576	9	0	0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	805	805	0	0
OutputsKnown_A	468092615	463372531	0	0
gen_no_flops.OutputDelay_A	468092615	463372531	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805	805	0	0
T1	1	1	0	0
T2	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463372531	0	0
T1	802861	802764	0	0
T2	589910	588929	0	0
T4	2988	2748	0	0
T5	2108	1925	0	0
T6	8340	8171	0	0
T16	5611	5385	0	0
T17	8730	8504	0	0
T18	3258	3032	0	0
T19	4882	4627	0	0
T20	1576	1492	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	463372531	0	0
T1	802861	802764	0	0
T2	589910	588929	0	0
T4	2988	2748	0	0
T5	2108	1925	0	0
T6	8340	8171	0	0
T16	5611	5385	0	0
T17	8730	8504	0	0
T18	3258	3032	0	0
T19	4882	4627	0	0
T20	1576	1492	0	0