Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T6
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	165446595	162748267	0	0
AllClkBypReqTrue_A	165446595	122670	0	0
IoClkBypReqFalse_A	165446595	162670354	0	2415
IoClkBypReqTrue_A	165446595	195771	0	0
LcClkBypAckFalse_A	165446595	162755525	0	0
LcClkBypAckTrue_A	165446595	115412	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162748267	0	0
T1	177947	177848	0	0
T2	60190	59178	0	0
T4	2868	2637	0	0
T5	2023	1634	0	0
T6	1584	1437	0	0
T16	1402	1230	0	0
T17	2094	2040	0	0
T18	3258	3031	0	0
T19	1215	1156	0	0
T20	1566	1486	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	122670	0	0
T1	177947	779	0	0
T2	60190	911	0	0
T5	2023	212	0	0
T6	1584	114	0	0
T16	1402	115	0	0
T17	2094	0	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	0	357	0	0
T23	0	179	0	0
T36	0	213	0	0
T65	0	40	0	0
T97	0	147	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162670354	0	2415
T1	177947	177813	0	3
T2	60190	59062	0	3
T4	2868	2635	0	3
T5	2023	1577	0	3
T6	1584	1401	0	3
T16	1402	1181	0	3
T17	2094	2038	0	3
T18	3258	3029	0	3
T19	1215	1154	0	3
T20	1566	1484	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	195771	0	0
T1	177947	1116	0	0
T2	60190	1017	0	0
T5	2023	267	0	0
T6	1584	148	0	0
T16	1402	162	0	0
T17	2094	0	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	0	498	0	0
T23	0	253	0	0
T36	0	92	0	0
T97	0	175	0	0
T98	0	116	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	162755525	0	0
T1	177947	177839	0	0
T2	60190	59488	0	0
T4	2868	2637	0	0
T5	2023	1676	0	0
T6	1584	1459	0	0
T16	1402	1228	0	0
T17	2094	2040	0	0
T18	3258	3031	0	0
T19	1215	1156	0	0
T20	1566	1486	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	115412	0	0
T1	177947	864	0	0
T2	60190	601	0	0
T5	2023	170	0	0
T6	1584	92	0	0
T16	1402	117	0	0
T17	2094	0	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	0	232	0	0
T23	0	233	0	0
T36	0	26	0	0
T97	0	89	0	0
T98	0	51	0	0