Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1872372164	15697	0	0
TransStop_A	1872372164	7954	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1872372164	15697	0	0
T1	3211444	127	0	0
T2	2359640	105	0	0
T3	0	3	0	0
T4	11956	34	0	0
T5	8436	0	0	0
T6	33360	0	0	0
T9	0	46	0	0
T11	0	12	0	0
T16	22444	0	0	0
T17	34924	4	0	0
T18	13036	33	0	0
T19	19528	0	0	0
T20	6308	0	0	0
T88	0	4	0	0
T99	0	4	0	0
T100	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1872372164	7954	0	0
T1	3211444	79	0	0
T2	2359640	50	0	0
T3	0	3	0	0
T4	11956	25	0	0
T5	8436	0	0	0
T6	33360	0	0	0
T9	0	30	0	0
T11	0	12	0	0
T16	22444	0	0	0
T17	34924	4	0	0
T18	13036	14	0	0
T19	19528	0	0	0
T20	6308	0	0	0
T88	0	4	0	0
T99	0	4	0	0
T100	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	468093041	3929	0	0
TransStop_A	468093041	1988	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468093041	3929	0	0
T1	802861	30	0	0
T2	589910	28	0	0
T4	2989	8	0	0
T5	2109	0	0	0
T6	8340	0	0	0
T9	0	10	0	0
T11	0	3	0	0
T16	5611	0	0	0
T17	8731	1	0	0
T18	3259	5	0	0
T19	4882	0	0	0
T20	1577	0	0	0
T88	0	1	0	0
T99	0	1	0	0
T100	0	5	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468093041	1988	0	0
T1	802861	17	0	0
T2	589910	13	0	0
T4	2989	5	0	0
T5	2109	0	0	0
T6	8340	0	0	0
T9	0	6	0	0
T11	0	3	0	0
T16	5611	0	0	0
T17	8731	1	0	0
T18	3259	3	0	0
T19	4882	0	0	0
T20	1577	0	0	0
T88	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	468093041	3963	0	0
TransStop_A	468093041	2010	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468093041	3963	0	0
T1	802861	34	0	0
T2	589910	28	0	0
T3	0	1	0	0
T4	2989	10	0	0
T5	2109	0	0	0
T6	8340	0	0	0
T9	0	11	0	0
T11	0	3	0	0
T16	5611	0	0	0
T17	8731	1	0	0
T18	3259	9	0	0
T19	4882	0	0	0
T20	1577	0	0	0
T88	0	1	0	0
T99	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468093041	2010	0	0
T1	802861	23	0	0
T2	589910	12	0	0
T3	0	1	0	0
T4	2989	8	0	0
T5	2109	0	0	0
T6	8340	0	0	0
T9	0	8	0	0
T11	0	3	0	0
T16	5611	0	0	0
T17	8731	1	0	0
T18	3259	3	0	0
T19	4882	0	0	0
T20	1577	0	0	0
T88	0	1	0	0
T99	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	468093041	3884	0	0
TransStop_A	468093041	1985	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468093041	3884	0	0
T1	802861	32	0	0
T2	589910	28	0	0
T3	0	1	0	0
T4	2989	9	0	0
T5	2109	0	0	0
T6	8340	0	0	0
T9	0	13	0	0
T11	0	3	0	0
T16	5611	0	0	0
T17	8731	1	0	0
T18	3259	11	0	0
T19	4882	0	0	0
T20	1577	0	0	0
T88	0	1	0	0
T99	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468093041	1985	0	0
T1	802861	21	0	0
T2	589910	14	0	0
T3	0	1	0	0
T4	2989	7	0	0
T5	2109	0	0	0
T6	8340	0	0	0
T9	0	9	0	0
T11	0	3	0	0
T16	5611	0	0	0
T17	8731	1	0	0
T18	3259	4	0	0
T19	4882	0	0	0
T20	1577	0	0	0
T88	0	1	0	0
T99	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	468093041	3921	0	0
TransStop_A	468093041	1971	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468093041	3921	0	0
T1	802861	31	0	0
T2	589910	21	0	0
T3	0	1	0	0
T4	2989	7	0	0
T5	2109	0	0	0
T6	8340	0	0	0
T9	0	12	0	0
T11	0	3	0	0
T16	5611	0	0	0
T17	8731	1	0	0
T18	3259	8	0	0
T19	4882	0	0	0
T20	1577	0	0	0
T88	0	1	0	0
T99	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468093041	1971	0	0
T1	802861	18	0	0
T2	589910	11	0	0
T3	0	1	0	0
T4	2989	5	0	0
T5	2109	0	0	0
T6	8340	0	0	0
T9	0	7	0	0
T11	0	3	0	0
T16	5611	0	0	0
T17	8731	1	0	0
T18	3259	4	0	0
T19	4882	0	0	0
T20	1577	0	0	0
T88	0	1	0	0
T99	0	1	0	0