Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_io_meas.u_timeout_err_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_sync.u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div2_meas.u_timeout_err_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div2_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_sync.u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_io_div4_meas.u_timeout_err_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_io_div4_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_sync.u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_main_meas.u_timeout_err_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_main_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_sync.u_sync 100.00 100.00 100.00



Module Instance : tb.dut.u_usb_meas.u_timeout_err_sync

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.44 100.00 83.33 100.00 u_usb_meas


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
g_sync.u_sync 100.00 100.00 100.00

Line Coverage for Module : prim_edge_detector
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
48 2 2
49 1 1
52 1 1
53 1 1


Cond Coverage for Module : prim_edge_detector
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T28
11CoveredT1,T2,T28

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T28
10CoveredT4,T5,T6
11CoveredT1,T2,T28

Branch Coverage for Module : prim_edge_detector
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 48 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_io_meas.u_timeout_err_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
48 2 2
49 1 1
52 1 1
53 1 1


Cond Coverage for Instance : tb.dut.u_io_meas.u_timeout_err_sync
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T28
11CoveredT1,T2,T28

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T28
10CoveredT4,T5,T6
11CoveredT1,T2,T28

Branch Coverage for Instance : tb.dut.u_io_meas.u_timeout_err_sync
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 48 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_timeout_err_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
48 2 2
49 1 1
52 1 1
53 1 1


Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_timeout_err_sync
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T28
11CoveredT1,T2,T28

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T28
10CoveredT4,T5,T6
11CoveredT1,T2,T28

Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_timeout_err_sync
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 48 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_timeout_err_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
48 2 2
49 1 1
52 1 1
53 1 1


Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_timeout_err_sync
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T28
11CoveredT1,T2,T28

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T28
10CoveredT4,T5,T6
11CoveredT1,T2,T28

Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_timeout_err_sync
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 48 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_main_meas.u_timeout_err_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
48 2 2
49 1 1
52 1 1
53 1 1


Cond Coverage for Instance : tb.dut.u_main_meas.u_timeout_err_sync
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T28
11CoveredT1,T2,T28

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T28
10CoveredT4,T5,T6
11CoveredT1,T2,T28

Branch Coverage for Instance : tb.dut.u_main_meas.u_timeout_err_sync
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 48 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

Line Coverage for Instance : tb.dut.u_usb_meas.u_timeout_err_sync
Line No.TotalCoveredPercent
TOTAL66100.00
CONT_ASSIGN4511100.00
ALWAYS4833100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
45 1 1
48 2 2
49 1 1
52 1 1
53 1 1


Cond Coverage for Instance : tb.dut.u_usb_meas.u_timeout_err_sync
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       52
 EXPRESSION (q_sync_d & ((~q_sync_q)))
             ----1---   ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT1,T2,T12
11CoveredT1,T2,T12

 LINE       53
 EXPRESSION (((~q_sync_d)) & q_sync_q)
             ------1------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T12
10CoveredT4,T5,T6
11CoveredT1,T2,T12

Branch Coverage for Instance : tb.dut.u_usb_meas.u_timeout_err_sync
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 48 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 48 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T4,T5,T6

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