Line Coverage for Module :
prim_edge_detector
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
ALWAYS | 48 | 3 | 3 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
45 |
1 |
1 |
48 |
2 |
2 |
49 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
Cond Coverage for Module :
prim_edge_detector
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 52
EXPRESSION (q_sync_d & ((~q_sync_q)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T28 |
1 | 1 | Covered | T1,T2,T28 |
LINE 53
EXPRESSION (((~q_sync_d)) & q_sync_q)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T28 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T1,T2,T28 |
Branch Coverage for Module :
prim_edge_detector
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
48 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 48 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_io_meas.u_timeout_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
ALWAYS | 48 | 3 | 3 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
45 |
1 |
1 |
48 |
2 |
2 |
49 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_meas.u_timeout_err_sync
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 52
EXPRESSION (q_sync_d & ((~q_sync_q)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T28 |
1 | 1 | Covered | T1,T2,T28 |
LINE 53
EXPRESSION (((~q_sync_d)) & q_sync_q)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T28 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T1,T2,T28 |
Branch Coverage for Instance : tb.dut.u_io_meas.u_timeout_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
48 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 48 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_timeout_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
ALWAYS | 48 | 3 | 3 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
45 |
1 |
1 |
48 |
2 |
2 |
49 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div2_meas.u_timeout_err_sync
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 52
EXPRESSION (q_sync_d & ((~q_sync_q)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T28 |
1 | 1 | Covered | T1,T2,T28 |
LINE 53
EXPRESSION (((~q_sync_d)) & q_sync_q)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T28 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T1,T2,T28 |
Branch Coverage for Instance : tb.dut.u_io_div2_meas.u_timeout_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
48 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 48 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_timeout_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
ALWAYS | 48 | 3 | 3 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
45 |
1 |
1 |
48 |
2 |
2 |
49 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_div4_meas.u_timeout_err_sync
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 52
EXPRESSION (q_sync_d & ((~q_sync_q)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T28 |
1 | 1 | Covered | T1,T2,T28 |
LINE 53
EXPRESSION (((~q_sync_d)) & q_sync_q)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T28 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T1,T2,T28 |
Branch Coverage for Instance : tb.dut.u_io_div4_meas.u_timeout_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
48 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 48 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_main_meas.u_timeout_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
ALWAYS | 48 | 3 | 3 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
45 |
1 |
1 |
48 |
2 |
2 |
49 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_main_meas.u_timeout_err_sync
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 52
EXPRESSION (q_sync_d & ((~q_sync_q)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T28 |
1 | 1 | Covered | T1,T2,T28 |
LINE 53
EXPRESSION (((~q_sync_d)) & q_sync_q)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T28 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T1,T2,T28 |
Branch Coverage for Instance : tb.dut.u_main_meas.u_timeout_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
48 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 48 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_timeout_err_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
ALWAYS | 48 | 3 | 3 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
45 |
1 |
1 |
48 |
2 |
2 |
49 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_usb_meas.u_timeout_err_sync
| Total | Covered | Percent |
Conditions | 6 | 6 | 100.00 |
Logical | 6 | 6 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 52
EXPRESSION (q_sync_d & ((~q_sync_q)))
----1--- ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T1,T2,T12 |
1 | 1 | Covered | T1,T2,T12 |
LINE 53
EXPRESSION (((~q_sync_d)) & q_sync_q)
------1------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T12 |
1 | 0 | Covered | T4,T5,T6 |
1 | 1 | Covered | T1,T2,T12 |
Branch Coverage for Instance : tb.dut.u_usb_meas.u_timeout_err_sync
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
48 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv' or '../src/lowrisc_prim_edge_detector_0.1/rtl/prim_edge_detector.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 48 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T5,T6 |
0 |
Covered |
T4,T5,T6 |