SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_clkmgr_byp.u_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_clkmgr_byp.u_lc_byp_req | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_clkmgr_byp |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 1610 | 1610 | 0 | 0 |
OutputsKnown_A | 330893190 | 325746686 | 0 | 0 |
gen_flops.OutputDelay_A | 330893190 | 325731766 | 0 | 4830 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1610 | 1610 | 0 | 0 |
T1 | 2 | 2 | 0 | 0 |
T2 | 2 | 2 | 0 | 0 |
T4 | 2 | 2 | 0 | 0 |
T5 | 2 | 2 | 0 | 0 |
T6 | 2 | 2 | 0 | 0 |
T16 | 2 | 2 | 0 | 0 |
T17 | 2 | 2 | 0 | 0 |
T18 | 2 | 2 | 0 | 0 |
T19 | 2 | 2 | 0 | 0 |
T20 | 2 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 330893190 | 325746686 | 0 | 0 |
T1 | 355894 | 355852 | 0 | 0 |
T2 | 120380 | 120188 | 0 | 0 |
T4 | 5736 | 5276 | 0 | 0 |
T5 | 4046 | 3694 | 0 | 0 |
T6 | 3168 | 3104 | 0 | 0 |
T16 | 2804 | 2692 | 0 | 0 |
T17 | 4188 | 4082 | 0 | 0 |
T18 | 6516 | 6064 | 0 | 0 |
T19 | 2430 | 2314 | 0 | 0 |
T20 | 3132 | 2974 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 330893190 | 325731766 | 0 | 4830 |
T1 | 355894 | 355848 | 0 | 6 |
T2 | 120380 | 120158 | 0 | 6 |
T4 | 5736 | 5270 | 0 | 6 |
T5 | 4046 | 3688 | 0 | 6 |
T6 | 3168 | 3098 | 0 | 6 |
T16 | 2804 | 2686 | 0 | 6 |
T17 | 4188 | 4076 | 0 | 6 |
T18 | 6516 | 6058 | 0 | 6 |
T19 | 2430 | 2308 | 0 | 6 |
T20 | 3132 | 2968 | 0 | 6 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 165446595 | 162873343 | 0 | 0 |
gen_flops.OutputDelay_A | 165446595 | 162865883 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 165446595 | 162873343 | 0 | 0 |
T1 | 177947 | 177926 | 0 | 0 |
T2 | 60190 | 60094 | 0 | 0 |
T4 | 2868 | 2638 | 0 | 0 |
T5 | 2023 | 1847 | 0 | 0 |
T6 | 1584 | 1552 | 0 | 0 |
T16 | 1402 | 1346 | 0 | 0 |
T17 | 2094 | 2041 | 0 | 0 |
T18 | 3258 | 3032 | 0 | 0 |
T19 | 1215 | 1157 | 0 | 0 |
T20 | 1566 | 1487 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 165446595 | 162865883 | 0 | 2415 |
T1 | 177947 | 177924 | 0 | 3 |
T2 | 60190 | 60079 | 0 | 3 |
T4 | 2868 | 2635 | 0 | 3 |
T5 | 2023 | 1844 | 0 | 3 |
T6 | 1584 | 1549 | 0 | 3 |
T16 | 1402 | 1343 | 0 | 3 |
T17 | 2094 | 2038 | 0 | 3 |
T18 | 3258 | 3029 | 0 | 3 |
T19 | 1215 | 1154 | 0 | 3 |
T20 | 1566 | 1484 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 805 | 805 | 0 | 0 |
OutputsKnown_A | 165446595 | 162873343 | 0 | 0 |
gen_flops.OutputDelay_A | 165446595 | 162865883 | 0 | 2415 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 805 | 805 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 165446595 | 162873343 | 0 | 0 |
T1 | 177947 | 177926 | 0 | 0 |
T2 | 60190 | 60094 | 0 | 0 |
T4 | 2868 | 2638 | 0 | 0 |
T5 | 2023 | 1847 | 0 | 0 |
T6 | 1584 | 1552 | 0 | 0 |
T16 | 1402 | 1346 | 0 | 0 |
T17 | 2094 | 2041 | 0 | 0 |
T18 | 3258 | 3032 | 0 | 0 |
T19 | 1215 | 1157 | 0 | 0 |
T20 | 1566 | 1487 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 165446595 | 162865883 | 0 | 2415 |
T1 | 177947 | 177924 | 0 | 3 |
T2 | 60190 | 60079 | 0 | 3 |
T4 | 2868 | 2635 | 0 | 3 |
T5 | 2023 | 1844 | 0 | 3 |
T6 | 1584 | 1549 | 0 | 3 |
T16 | 1402 | 1343 | 0 | 3 |
T17 | 2094 | 2038 | 0 | 3 |
T18 | 3258 | 3029 | 0 | 3 |
T19 | 1215 | 1154 | 0 | 3 |
T20 | 1566 | 1484 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |