Module Definition
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Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.04 100.00 96.15 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.55 100.00 98.21 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.91 100.00 99.65 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_shadow
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Module : prim_subreg_shadow
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT48,T49,T50
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT48,T49,T50
10CoveredT1,T24,T27

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110CoveredT48,T49,T50
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT48,T49,T50
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT48,T49,T50

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT48,T49,T50

Branch Coverage for Module : prim_subreg_shadow
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T24,T27
0 0 0 Covered T4,T5,T6


Assert Coverage for Module : prim_subreg_shadow
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 10100 10100 0 0
MubiIsNotYetSupported_A 2147483647 2147483647 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 10100 10100 0 0
T1 10 10 0 0
T2 10 10 0 0
T4 10 10 0 0
T5 10 10 0 0
T6 10 10 0 0
T16 10 10 0 0
T17 10 10 0 0
T18 10 10 0 0
T19 10 10 0 0
T20 10 10 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 5054776 5054236 0 0
T2 3531370 3525748 0 0
T4 18744 17368 0 0
T5 13578 12476 0 0
T6 54560 53530 0 0
T16 36118 34890 0 0
T17 54992 53746 0 0
T18 20476 19166 0 0
T19 30856 29446 0 0
T20 9746 9278 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT49,T50,T51
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT48,T49,T50
10CoveredT1,T24,T27

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110CoveredT49,T50,T51
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT48,T49,T50
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT48,T49,T50

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT48,T49,T50

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T24,T27
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_hi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 441544108 436881561 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T2 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441544108 436881561 0 0
T1 764386 764293 0 0
T2 508696 507753 0 0
T4 2868 2638 0 0
T5 2023 1847 0 0
T6 8006 7844 0 0
T16 5386 5169 0 0
T17 8381 8164 0 0
T18 3129 2912 0 0
T19 4737 4492 0 0
T20 1467 1387 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT48,T49,T50
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT48,T49,T50
10CoveredT1,T24,T27

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110CoveredT48,T49,T50
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT49,T50,T51
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT49,T50,T51

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT48,T49,T50

Branch Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T24,T27
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_io_meas_ctrl_shadowed_lo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 441544108 436881561 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T2 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 441544108 436881561 0 0
T1 764386 764293 0 0
T2 508696 507753 0 0
T4 2868 2638 0 0
T5 2023 1847 0 0
T6 8006 7844 0 0
T16 5386 5169 0 0
T17 8381 8164 0 0
T18 3129 2912 0 0
T19 4737 4492 0 0
T20 1467 1387 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT49,T50,T52
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT48,T49,T50
10CoveredT1,T24,T27

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110CoveredT49,T50,T52
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT49,T50,T53
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT49,T50,T53

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT48,T49,T50

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T24,T27
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_hi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 219828736 218693966 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T2 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 219828736 218693966 0 0
T1 382407 382384 0 0
T2 257866 257590 0 0
T4 1388 1319 0 0
T5 1098 1029 0 0
T6 4621 4552 0 0
T16 2913 2872 0 0
T17 4130 4082 0 0
T18 1525 1456 0 0
T19 2301 2246 0 0
T20 714 693 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT49,T50,T51
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT48,T49,T50
10CoveredT1,T24,T27

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110CoveredT49,T50,T51
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT49,T50,T53
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT49,T50,T53

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT48,T49,T50

Branch Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T24,T27
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_io_div2_meas_ctrl_shadowed_lo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 219828736 218693966 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T2 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 219828736 218693966 0 0
T1 382407 382384 0 0
T2 257866 257590 0 0
T4 1388 1319 0 0
T5 1098 1029 0 0
T6 4621 4552 0 0
T16 2913 2872 0 0
T17 4130 4082 0 0
T18 1525 1456 0 0
T19 2301 2246 0 0
T20 714 693 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT49,T54,T55
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT49,T50,T52
10CoveredT1,T24,T27

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110CoveredT49,T54,T55
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT49,T56,T51
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT49,T56,T51

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT49,T50,T52

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T24,T27
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_hi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 109913787 109346525 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T2 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 109913787 109346525 0 0
T1 191203 191192 0 0
T2 128932 128794 0 0
T4 694 660 0 0
T5 548 513 0 0
T6 2310 2276 0 0
T16 1456 1435 0 0
T17 2065 2041 0 0
T18 762 728 0 0
T19 1151 1123 0 0
T20 357 347 0 0

Line Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT49,T54,T57
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT49,T50,T56
10CoveredT1,T24,T27

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110CoveredT49,T54,T57
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT56,T51,T52
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT56,T51,T52

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT49,T50,T56

Branch Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T24,T27
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_io_div4_meas_ctrl_shadowed_lo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 109913787 109346525 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T2 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 109913787 109346525 0 0
T1 191203 191192 0 0
T2 128932 128794 0 0
T4 694 660 0 0
T5 548 513 0 0
T6 2310 2276 0 0
T16 1456 1435 0 0
T17 2065 2041 0 0
T18 762 728 0 0
T19 1151 1123 0 0
T20 357 347 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT50,T56,T54
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT50,T56,T51
10CoveredT1,T24,T27

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110CoveredT50,T56,T54
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT50,T53,T58
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT50,T53,T58

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT50,T56,T51

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T24,T27
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_hi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 471054484 466142080 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T2 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 471054484 466142080 0 0
T1 802861 802764 0 0
T2 589910 588929 0 0
T4 2988 2748 0 0
T5 2108 1925 0 0
T6 8340 8171 0 0
T16 5611 5385 0 0
T17 8730 8504 0 0
T18 3258 3032 0 0
T19 4882 4627 0 0
T20 1576 1492 0 0

Line Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT50,T56,T53
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT48,T50,T56
10CoveredT1,T24,T27

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110CoveredT50,T56,T53
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT53,T58,T55
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT53,T58,T55

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT48,T50,T56

Branch Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T24,T27
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_main_meas_ctrl_shadowed_lo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 471054484 466142080 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T2 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 471054484 466142080 0 0
T1 802861 802764 0 0
T2 589910 588929 0 0
T4 2988 2748 0 0
T5 2108 1925 0 0
T6 8340 8171 0 0
T16 5611 5385 0 0
T17 8730 8504 0 0
T18 3258 3032 0 0
T19 4882 4627 0 0
T20 1576 1492 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT49,T50,T52
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT49,T50,T52
10CoveredT1,T24,T27

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110CoveredT49,T50,T52
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT50,T52,T55
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT50,T52,T55

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT49,T50,T52

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T24,T27
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_hi
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 226192637 223832873 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T2 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 226192637 223832873 0 0
T1 386531 386485 0 0
T2 280281 279808 0 0
T4 1434 1319 0 0
T5 1012 924 0 0
T6 4003 3922 0 0
T16 2693 2584 0 0
T17 4190 4082 0 0
T18 1564 1455 0 0
T19 2357 2235 0 0
T20 759 720 0 0

Line Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
94 1 1
100 1 1
101 1 1
102 1 1
103 1 1
104 1 1
105 1 1
MISSING_ELSE
113 1 1
114 unreachable
138 1 1
139 unreachable
160 1 1
161 unreachable
180 1 1
183 1 1
184 1 1
187 1 1
188 1 1
189 1 1


Cond Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
TotalCoveredPercent
Conditions262596.15
Logical262596.15
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT50,T53,T58
11CoveredT1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT4,T5,T6
01CoveredT49,T50,T52
10CoveredT1,T24,T27

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101CoveredT1,T2,T3
110CoveredT50,T53,T58
111CoveredT1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT4,T5,T6
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT49,T50,T52
1110Not Covered
1111CoveredT1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T5,T6

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT49,T50,T52

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT4,T5,T6
1CoveredT49,T50,T52

Branch Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_shadow.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 183 (((~staged_q) != wr_data)) ?

Branches:
-1-StatusTests
1 Covered T4,T5,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 100 if ((!rst_ni)) -2-: 102 if ((wr_en && (!err_storage))) -3-: 104 if ((phase_clear || err_storage))

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T6
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T24,T27
0 0 0 Covered T4,T5,T6


Assert Coverage for Instance : tb.dut.u_reg.u_usb_meas_ctrl_shadowed_lo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1010 1010 0 0
MubiIsNotYetSupported_A 226192637 223832873 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1010 1010 0 0
T1 1 1 0 0
T2 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 226192637 223832873 0 0
T1 386531 386485 0 0
T2 280281 279808 0 0
T4 1434 1319 0 0
T5 1012 924 0 0
T6 4003 3922 0 0
T16 2693 2584 0 0
T17 4190 4082 0 0
T18 1564 1455 0 0
T19 2357 2235 0 0
T20 759 720 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%