Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	165446595	18716626	0	58

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	18716626	0	58
T1	177947	9799	0	0
T2	60190	3762	0	0
T3	0	3528	0	0
T9	0	59612	0	0
T10	0	22772	0	1
T11	0	60859	0	0
T12	0	130707	0	0
T13	0	949289	0	0
T14	0	27294	0	0
T15	0	25590	0	0
T16	1402	0	0	0
T17	2094	0	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	2658	0	0	0
T23	2066	0	0	0
T26	0	0	0	1
T101	0	0	0	1
T102	0	0	0	1
T103	0	0	0	1
T104	0	0	0	1
T105	0	0	0	1
T106	0	0	0	1
T107	0	0	0	1
T108	0	0	0	1