Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	166352260	5420608	0	0
clk_enables_rd_A	166352260	39897	0	0
clk_hints_rd_A	166352260	35721	0	0
extclk_ctrl_rd_A	166352260	44583	0	0
extclk_ctrl_regwen_rd_A	166352260	34367	0	0
jitter_enable_rd_A	166352260	51053	0	0
jitter_regwen_rd_A	166352260	37903	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166352260	5420608	0	0
T1	177947	86621	0	0
T2	60190	0	0	0
T12	0	209409	0	0
T13	0	61703	0	0
T15	0	82373	0	0
T16	1402	0	0	0
T17	2094	0	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	2658	0	0	0
T23	2066	0	0	0
T59	0	180310	0	0
T60	0	117114	0	0
T61	0	146588	0	0
T62	0	117317	0	0
T63	0	85534	0	0
T64	0	99259	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166352260	39897	0	0
T2	60190	11	0	0
T9	0	5	0	0
T13	0	2420	0	0
T15	0	3033	0	0
T16	1402	0	0	0
T17	2094	0	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	2658	0	0	0
T23	2066	0	0	0
T66	1013	0	0	0
T88	0	1	0	0
T124	0	2	0	0
T125	0	10	0	0
T126	0	11	0	0
T127	0	21	0	0
T128	0	16	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166352260	35721	0	0
T2	60190	9	0	0
T9	0	7	0	0
T13	0	2104	0	0
T15	0	2719	0	0
T16	1402	0	0	0
T17	2094	1	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	2658	0	0	0
T23	2066	0	0	0
T66	1013	0	0	0
T88	0	7	0	0
T124	0	5	0	0
T125	0	10	0	0
T126	0	12	0	0
T129	0	5	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166352260	44583	0	0
T1	177947	0	0	0
T2	60190	81	0	0
T5	2023	1	0	0
T6	1584	0	0	0
T16	1402	0	0	0
T17	2094	0	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	0	52	0	0
T23	0	59	0	0
T24	0	77	0	0
T65	0	22	0	0
T97	0	15	0	0
T130	0	39	0	0
T131	0	15	0	0
T132	0	16	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166352260	34367	0	0
T9	364749	0	0	0
T13	0	2146	0	0
T15	0	2953	0	0
T24	55719	36	0	0
T27	64560	0	0	0
T28	61073	0	0	0
T36	2005	0	0	0
T63	0	3033	0	0
T88	1701	0	0	0
T96	0	13	0	0
T97	1501	0	0	0
T98	1662	0	0	0
T99	1719	0	0	0
T133	0	7	0	0
T134	0	37	0	0
T135	0	418	0	0
T136	0	5955	0	0
T137	0	3631	0	0
T138	1121	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166352260	51053	0	0
T2	60190	339	0	0
T9	0	250	0	0
T13	0	2477	0	0
T15	0	4522	0	0
T16	1402	0	0	0
T17	2094	110	0	0
T18	3258	0	0	0
T19	1215	0	0	0
T20	1566	0	0	0
T21	1660	0	0	0
T22	2658	0	0	0
T23	2066	0	0	0
T66	1013	0	0	0
T88	0	39	0	0
T124	0	112	0	0
T125	0	116	0	0
T126	0	426	0	0
T129	0	96	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	166352260	37903	0	0
T13	208610	2125	0	0
T14	174298	0	0	0
T15	0	3033	0	0
T32	748	0	0	0
T40	1413	0	0	0
T41	3066	0	0	0
T42	2286	0	0	0
T43	1007	0	0	0
T44	2420	0	0	0
T45	1689	0	0	0
T63	0	3779	0	0
T135	0	618	0	0
T136	0	6608	0	0
T137	0	3836	0	0
T139	0	514	0	0
T140	0	3643	0	0
T141	0	2222	0	0
T142	0	1413	0	0
T143	1308	0	0	0