Module Definition
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Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T1
11CoveredT5,T6,T1

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 438701257 4157 0 0
g_div2.Div2Whole_A 438701257 4985 0 0
g_div4.Div4Stepped_A 218453498 4066 0 0
g_div4.Div4Whole_A 218453498 4669 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438701257 4157 0 0
T1 764386 33 0 0
T2 508697 24 0 0
T5 2024 5 0 0
T6 8006 7 0 0
T16 5387 5 0 0
T17 8381 0 0 0
T18 3129 0 0 0
T19 4737 0 0 0
T20 1467 0 0 0
T21 1547 0 0 0
T22 0 9 0 0
T23 0 10 0 0
T65 0 1 0 0
T97 0 4 0 0
T98 0 2 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438701257 4985 0 0
T1 764386 36 0 0
T2 508697 25 0 0
T5 2024 6 0 0
T6 8006 7 0 0
T16 5387 6 0 0
T17 8381 0 0 0
T18 3129 0 0 0
T19 4737 0 0 0
T20 1467 0 0 0
T21 1547 0 0 0
T22 0 9 0 0
T23 0 10 0 0
T65 0 2 0 0
T97 0 4 0 0
T98 0 3 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 218453498 4066 0 0
T1 382407 33 0 0
T2 257867 24 0 0
T5 1098 5 0 0
T6 4621 7 0 0
T16 2913 5 0 0
T17 4131 0 0 0
T18 1525 0 0 0
T19 2302 0 0 0
T20 715 0 0 0
T21 714 0 0 0
T22 0 9 0 0
T23 0 10 0 0
T65 0 1 0 0
T97 0 4 0 0
T98 0 2 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 218453498 4669 0 0
T1 382407 36 0 0
T2 257867 25 0 0
T5 1098 5 0 0
T6 4621 7 0 0
T16 2913 6 0 0
T17 4131 0 0 0
T18 1525 0 0 0
T19 2302 0 0 0
T20 715 0 0 0
T21 714 0 0 0
T22 0 8 0 0
T23 0 10 0 0
T65 0 2 0 0
T97 0 4 0 0
T98 0 3 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T1
11CoveredT5,T6,T1

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 438701257 4157 0 0
g_div2.Div2Whole_A 438701257 4985 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438701257 4157 0 0
T1 764386 33 0 0
T2 508697 24 0 0
T5 2024 5 0 0
T6 8006 7 0 0
T16 5387 5 0 0
T17 8381 0 0 0
T18 3129 0 0 0
T19 4737 0 0 0
T20 1467 0 0 0
T21 1547 0 0 0
T22 0 9 0 0
T23 0 10 0 0
T65 0 1 0 0
T97 0 4 0 0
T98 0 2 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 438701257 4985 0 0
T1 764386 36 0 0
T2 508697 25 0 0
T5 2024 6 0 0
T6 8006 7 0 0
T16 5387 6 0 0
T17 8381 0 0 0
T18 3129 0 0 0
T19 4737 0 0 0
T20 1467 0 0 0
T21 1547 0 0 0
T22 0 9 0 0
T23 0 10 0 0
T65 0 2 0 0
T97 0 4 0 0
T98 0 3 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT4,T5,T6
10CoveredT5,T6,T1
11CoveredT5,T6,T1

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 218453498 4066 0 0
g_div4.Div4Whole_A 218453498 4669 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 218453498 4066 0 0
T1 382407 33 0 0
T2 257867 24 0 0
T5 1098 5 0 0
T6 4621 7 0 0
T16 2913 5 0 0
T17 4131 0 0 0
T18 1525 0 0 0
T19 2302 0 0 0
T20 715 0 0 0
T21 714 0 0 0
T22 0 9 0 0
T23 0 10 0 0
T65 0 1 0 0
T97 0 4 0 0
T98 0 2 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 218453498 4669 0 0
T1 382407 36 0 0
T2 257867 25 0 0
T5 1098 5 0 0
T6 4621 7 0 0
T16 2913 6 0 0
T17 4131 0 0 0
T18 1525 0 0 0
T19 2302 0 0 0
T20 715 0 0 0
T21 714 0 0 0
T22 0 8 0 0
T23 0 10 0 0
T65 0 2 0 0
T97 0 4 0 0
T98 0 3 0 0

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