SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.clkmgr_div2_sva_if | 100.00 | 100.00 | 100.00 | 100.00 | |||
tb.dut.clkmgr_div4_sva_if | 100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.65 | 100.00 | 93.24 | 100.00 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T5,T6,T1 |
1 | 1 | Covered | T5,T6,T1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 438701257 | 4157 | 0 | 0 |
g_div2.Div2Whole_A | 438701257 | 4985 | 0 | 0 |
g_div4.Div4Stepped_A | 218453498 | 4066 | 0 | 0 |
g_div4.Div4Whole_A | 218453498 | 4669 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 438701257 | 4157 | 0 | 0 |
T1 | 764386 | 33 | 0 | 0 |
T2 | 508697 | 24 | 0 | 0 |
T5 | 2024 | 5 | 0 | 0 |
T6 | 8006 | 7 | 0 | 0 |
T16 | 5387 | 5 | 0 | 0 |
T17 | 8381 | 0 | 0 | 0 |
T18 | 3129 | 0 | 0 | 0 |
T19 | 4737 | 0 | 0 | 0 |
T20 | 1467 | 0 | 0 | 0 |
T21 | 1547 | 0 | 0 | 0 |
T22 | 0 | 9 | 0 | 0 |
T23 | 0 | 10 | 0 | 0 |
T65 | 0 | 1 | 0 | 0 |
T97 | 0 | 4 | 0 | 0 |
T98 | 0 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 438701257 | 4985 | 0 | 0 |
T1 | 764386 | 36 | 0 | 0 |
T2 | 508697 | 25 | 0 | 0 |
T5 | 2024 | 6 | 0 | 0 |
T6 | 8006 | 7 | 0 | 0 |
T16 | 5387 | 6 | 0 | 0 |
T17 | 8381 | 0 | 0 | 0 |
T18 | 3129 | 0 | 0 | 0 |
T19 | 4737 | 0 | 0 | 0 |
T20 | 1467 | 0 | 0 | 0 |
T21 | 1547 | 0 | 0 | 0 |
T22 | 0 | 9 | 0 | 0 |
T23 | 0 | 10 | 0 | 0 |
T65 | 0 | 2 | 0 | 0 |
T97 | 0 | 4 | 0 | 0 |
T98 | 0 | 3 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 218453498 | 4066 | 0 | 0 |
T1 | 382407 | 33 | 0 | 0 |
T2 | 257867 | 24 | 0 | 0 |
T5 | 1098 | 5 | 0 | 0 |
T6 | 4621 | 7 | 0 | 0 |
T16 | 2913 | 5 | 0 | 0 |
T17 | 4131 | 0 | 0 | 0 |
T18 | 1525 | 0 | 0 | 0 |
T19 | 2302 | 0 | 0 | 0 |
T20 | 715 | 0 | 0 | 0 |
T21 | 714 | 0 | 0 | 0 |
T22 | 0 | 9 | 0 | 0 |
T23 | 0 | 10 | 0 | 0 |
T65 | 0 | 1 | 0 | 0 |
T97 | 0 | 4 | 0 | 0 |
T98 | 0 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 218453498 | 4669 | 0 | 0 |
T1 | 382407 | 36 | 0 | 0 |
T2 | 257867 | 25 | 0 | 0 |
T5 | 1098 | 5 | 0 | 0 |
T6 | 4621 | 7 | 0 | 0 |
T16 | 2913 | 6 | 0 | 0 |
T17 | 4131 | 0 | 0 | 0 |
T18 | 1525 | 0 | 0 | 0 |
T19 | 2302 | 0 | 0 | 0 |
T20 | 715 | 0 | 0 | 0 |
T21 | 714 | 0 | 0 | 0 |
T22 | 0 | 8 | 0 | 0 |
T23 | 0 | 10 | 0 | 0 |
T65 | 0 | 2 | 0 | 0 |
T97 | 0 | 4 | 0 | 0 |
T98 | 0 | 3 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T5,T6,T1 |
1 | 1 | Covered | T5,T6,T1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div2.Div2Stepped_A | 438701257 | 4157 | 0 | 0 |
g_div2.Div2Whole_A | 438701257 | 4985 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 438701257 | 4157 | 0 | 0 |
T1 | 764386 | 33 | 0 | 0 |
T2 | 508697 | 24 | 0 | 0 |
T5 | 2024 | 5 | 0 | 0 |
T6 | 8006 | 7 | 0 | 0 |
T16 | 5387 | 5 | 0 | 0 |
T17 | 8381 | 0 | 0 | 0 |
T18 | 3129 | 0 | 0 | 0 |
T19 | 4737 | 0 | 0 | 0 |
T20 | 1467 | 0 | 0 | 0 |
T21 | 1547 | 0 | 0 | 0 |
T22 | 0 | 9 | 0 | 0 |
T23 | 0 | 10 | 0 | 0 |
T65 | 0 | 1 | 0 | 0 |
T97 | 0 | 4 | 0 | 0 |
T98 | 0 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 438701257 | 4985 | 0 | 0 |
T1 | 764386 | 36 | 0 | 0 |
T2 | 508697 | 25 | 0 | 0 |
T5 | 2024 | 6 | 0 | 0 |
T6 | 8006 | 7 | 0 | 0 |
T16 | 5387 | 6 | 0 | 0 |
T17 | 8381 | 0 | 0 | 0 |
T18 | 3129 | 0 | 0 | 0 |
T19 | 4737 | 0 | 0 | 0 |
T20 | 1467 | 0 | 0 | 0 |
T21 | 1547 | 0 | 0 | 0 |
T22 | 0 | 9 | 0 | 0 |
T23 | 0 | 10 | 0 | 0 |
T65 | 0 | 2 | 0 | 0 |
T97 | 0 | 4 | 0 | 0 |
T98 | 0 | 3 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 25 | 1 | 1 | 100.00 |
ALWAYS | 28 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
25 | 1 | 1 | |
28 | 1 | 1 |
Total | Covered | Percent | |
---|---|---|---|
Conditions | 3 | 3 | 100.00 |
Logical | 3 | 3 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 |
LINE 25 EXPRESSION (div_step_down_req_i && ((!scanmode))) ---------1--------- ------2------
-1- | -2- | Status | Tests |
---|---|---|---|
0 | 1 | Covered | T4,T5,T6 |
1 | 0 | Covered | T5,T6,T1 |
1 | 1 | Covered | T5,T6,T1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
g_div4.Div4Stepped_A | 218453498 | 4066 | 0 | 0 |
g_div4.Div4Whole_A | 218453498 | 4669 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 218453498 | 4066 | 0 | 0 |
T1 | 382407 | 33 | 0 | 0 |
T2 | 257867 | 24 | 0 | 0 |
T5 | 1098 | 5 | 0 | 0 |
T6 | 4621 | 7 | 0 | 0 |
T16 | 2913 | 5 | 0 | 0 |
T17 | 4131 | 0 | 0 | 0 |
T18 | 1525 | 0 | 0 | 0 |
T19 | 2302 | 0 | 0 | 0 |
T20 | 715 | 0 | 0 | 0 |
T21 | 714 | 0 | 0 | 0 |
T22 | 0 | 9 | 0 | 0 |
T23 | 0 | 10 | 0 | 0 |
T65 | 0 | 1 | 0 | 0 |
T97 | 0 | 4 | 0 | 0 |
T98 | 0 | 2 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 218453498 | 4669 | 0 | 0 |
T1 | 382407 | 36 | 0 | 0 |
T2 | 257867 | 25 | 0 | 0 |
T5 | 1098 | 5 | 0 | 0 |
T6 | 4621 | 7 | 0 | 0 |
T16 | 2913 | 6 | 0 | 0 |
T17 | 4131 | 0 | 0 | 0 |
T18 | 1525 | 0 | 0 | 0 |
T19 | 2302 | 0 | 0 | 0 |
T20 | 715 | 0 | 0 | 0 |
T21 | 714 | 0 | 0 | 0 |
T22 | 0 | 8 | 0 | 0 |
T23 | 0 | 10 | 0 | 0 |
T65 | 0 | 2 | 0 | 0 |
T97 | 0 | 4 | 0 | 0 |
T98 | 0 | 3 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |