Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	496339785	466	0	0
StatusRise_A	496339785	466	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496339785	466	0	0
T3	49071	0	0	0
T19	3645	12	0	0
T20	4698	7	0	0
T21	4980	15	0	0
T22	7974	0	0	0
T23	6198	0	0	0
T24	167157	0	0	0
T43	0	11	0	0
T65	5679	0	0	0
T66	3039	12	0	0
T98	4986	0	0	0
T144	0	5	0	0
T145	0	2	0	0
T146	0	13	0	0
T147	0	11	0	0
T148	0	5	0	0
T149	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	496339785	466	0	0
T3	49071	0	0	0
T19	3645	12	0	0
T20	4698	7	0	0
T21	4980	15	0	0
T22	7974	0	0	0
T23	6198	0	0	0
T24	167157	0	0	0
T43	0	11	0	0
T65	5679	0	0	0
T66	3039	12	0	0
T98	4986	0	0	0
T144	0	5	0	0
T145	0	2	0	0
T146	0	13	0	0
T147	0	11	0	0
T148	0	5	0	0
T149	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	165446595	161	0	0
StatusRise_A	165446595	161	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	161	0	0
T3	16357	0	0	0
T19	1215	3	0	0
T20	1566	4	0	0
T21	1660	6	0	0
T22	2658	0	0	0
T23	2066	0	0	0
T24	55719	0	0	0
T43	0	3	0	0
T65	1893	0	0	0
T66	1013	4	0	0
T98	1662	0	0	0
T144	0	2	0	0
T145	0	1	0	0
T146	0	6	0	0
T147	0	4	0	0
T148	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	161	0	0
T3	16357	0	0	0
T19	1215	3	0	0
T20	1566	4	0	0
T21	1660	6	0	0
T22	2658	0	0	0
T23	2066	0	0	0
T24	55719	0	0	0
T43	0	3	0	0
T65	1893	0	0	0
T66	1013	4	0	0
T98	1662	0	0	0
T144	0	2	0	0
T145	0	1	0	0
T146	0	6	0	0
T147	0	4	0	0
T148	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	165446595	149	0	0
StatusRise_A	165446595	149	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	149	0	0
T3	16357	0	0	0
T19	1215	4	0	0
T20	1566	1	0	0
T21	1660	6	0	0
T22	2658	0	0	0
T23	2066	0	0	0
T24	55719	0	0	0
T43	0	4	0	0
T65	1893	0	0	0
T66	1013	4	0	0
T98	1662	0	0	0
T144	0	1	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	149	0	0
T3	16357	0	0	0
T19	1215	4	0	0
T20	1566	1	0	0
T21	1660	6	0	0
T22	2658	0	0	0
T23	2066	0	0	0
T24	55719	0	0	0
T43	0	4	0	0
T65	1893	0	0	0
T66	1013	4	0	0
T98	1662	0	0	0
T144	0	1	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	165446595	156	0	0
StatusRise_A	165446595	156	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	156	0	0
T3	16357	0	0	0
T19	1215	5	0	0
T20	1566	2	0	0
T21	1660	3	0	0
T22	2658	0	0	0
T23	2066	0	0	0
T24	55719	0	0	0
T43	0	4	0	0
T65	1893	0	0	0
T66	1013	4	0	0
T98	1662	0	0	0
T144	0	2	0	0
T145	0	1	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165446595	156	0	0
T3	16357	0	0	0
T19	1215	5	0	0
T20	1566	2	0	0
T21	1660	3	0	0
T22	2658	0	0	0
T23	2066	0	0	0
T24	55719	0	0	0
T43	0	4	0	0
T65	1893	0	0	0
T66	1013	4	0	0
T98	1662	0	0	0
T144	0	2	0	0
T145	0	1	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0