Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48770	0	0
CgEnOn_A	2147483647	39133	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48770	0	0
T1	4935971	344	0	0
T2	3535415	92	0	0
T3	316030	1	0	0
T4	18336	21	0	0
T5	13113	3	0	0
T6	52300	3	0	0
T9	0	10	0	0
T16	34892	3	0	0
T17	53686	8	0	0
T18	20012	17	0	0
T19	52686	44	0	0
T20	16764	23	0	0
T21	7293	48	0	0
T22	12958	0	0	0
T23	83297	0	0	0
T24	237966	0	0	0
T43	0	23	0	0
T65	8727	0	0	0
T66	15782	32	0	0
T98	7944	0	0	0
T144	0	7	0	0
T145	0	1	0	0
T146	0	21	0	0
T147	0	19	0	0
T148	0	11	0	0
T149	0	10	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39133	0	0
T1	4935971	478	0	0
T2	3535415	133	0	0
T3	316030	41	0	0
T4	11952	34	0	0
T5	8432	0	0	0
T6	33360	0	0	0
T9	0	126	0	0
T16	34892	0	0	0
T17	53686	8	0	0
T18	20012	33	0	0
T19	52686	60	0	0
T20	16764	36	0	0
T21	10708	90	0	0
T22	19042	0	0	0
T23	122536	0	0	0
T24	237966	0	0	0
T43	0	30	0	0
T65	8727	0	0	0
T66	15782	64	0	0
T98	7944	0	0	0
T99	0	4	0	0
T144	0	11	0	0
T145	0	3	0	0
T146	0	31	0	0
T147	0	27	0	0
T148	0	14	0	0
T149	0	10	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	218453085	157	0	0
CgEnOn_A	218453085	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218453085	157	0	0
T3	32627	0	0	0
T19	2301	4	0	0
T20	714	1	0	0
T21	713	6	0	0
T22	1454	0	0	0
T23	9636	0	0	0
T24	15320	0	0	0
T43	0	4	0	0
T65	886	0	0	0
T66	1615	4	0	0
T98	821	0	0	0
T144	0	1	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218453085	157	0	0
T3	32627	0	0	0
T19	2301	4	0	0
T20	714	1	0	0
T21	713	6	0	0
T22	1454	0	0	0
T23	9636	0	0	0
T24	15320	0	0	0
T43	0	4	0	0
T65	886	0	0	0
T66	1615	4	0	0
T98	821	0	0	0
T144	0	1	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	109225953	157	0	0
CgEnOn_A	109225953	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109225953	157	0	0
T3	16314	0	0	0
T19	1151	4	0	0
T20	357	1	0	0
T21	357	6	0	0
T22	725	0	0	0
T23	4817	0	0	0
T24	7660	0	0	0
T43	0	4	0	0
T65	443	0	0	0
T66	808	4	0	0
T98	411	0	0	0
T144	0	1	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109225953	157	0	0
T3	16314	0	0	0
T19	1151	4	0	0
T20	357	1	0	0
T21	357	6	0	0
T22	725	0	0	0
T23	4817	0	0	0
T24	7660	0	0	0
T43	0	4	0	0
T65	443	0	0	0
T66	808	4	0	0
T98	411	0	0	0
T144	0	1	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	109225953	157	0	0
CgEnOn_A	109225953	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109225953	157	0	0
T3	16314	0	0	0
T19	1151	4	0	0
T20	357	1	0	0
T21	357	6	0	0
T22	725	0	0	0
T23	4817	0	0	0
T24	7660	0	0	0
T43	0	4	0	0
T65	443	0	0	0
T66	808	4	0	0
T98	411	0	0	0
T144	0	1	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109225953	157	0	0
T3	16314	0	0	0
T19	1151	4	0	0
T20	357	1	0	0
T21	357	6	0	0
T22	725	0	0	0
T23	4817	0	0	0
T24	7660	0	0	0
T43	0	4	0	0
T65	443	0	0	0
T66	808	4	0	0
T98	411	0	0	0
T144	0	1	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	109225953	157	0	0
CgEnOn_A	109225953	157	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109225953	157	0	0
T3	16314	0	0	0
T19	1151	4	0	0
T20	357	1	0	0
T21	357	6	0	0
T22	725	0	0	0
T23	4817	0	0	0
T24	7660	0	0	0
T43	0	4	0	0
T65	443	0	0	0
T66	808	4	0	0
T98	411	0	0	0
T144	0	1	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109225953	157	0	0
T3	16314	0	0	0
T19	1151	4	0	0
T20	357	1	0	0
T21	357	6	0	0
T22	725	0	0	0
T23	4817	0	0	0
T24	7660	0	0	0
T43	0	4	0	0
T65	443	0	0	0
T66	808	4	0	0
T98	411	0	0	0
T144	0	1	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	438700817	157	0	0
CgEnOn_A	438700817	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438700817	157	0	0
T3	65429	0	0	0
T19	4737	4	0	0
T20	1467	1	0	0
T21	1547	6	0	0
T22	2604	0	0	0
T23	16524	0	0	0
T24	55719	0	0	0
T43	0	4	0	0
T65	1818	0	0	0
T66	3282	4	0	0
T98	1644	0	0	0
T144	0	1	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438700817	151	0	0
T3	65429	0	0	0
T19	4737	4	0	0
T20	1467	1	0	0
T21	1547	6	0	0
T22	2604	0	0	0
T23	16524	0	0	0
T24	55719	0	0	0
T43	0	4	0	0
T65	1818	0	0	0
T66	3282	4	0	0
T98	1644	0	0	0
T144	0	1	0	0
T146	0	3	0	0
T147	0	3	0	0
T148	0	2	0	0
T149	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	468092615	165	0	0
CgEnOn_A	468092615	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	165	0	0
T3	68158	0	0	0
T19	4882	3	0	0
T20	1576	4	0	0
T21	1582	6	0	0
T22	2712	0	0	0
T23	17212	0	0	0
T24	58043	0	0	0
T43	0	3	0	0
T65	1893	0	0	0
T66	3394	4	0	0
T98	1712	0	0	0
T144	0	2	0	0
T145	0	1	0	0
T146	0	6	0	0
T147	0	4	0	0
T148	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	161	0	0
T3	68158	0	0	0
T19	4882	3	0	0
T20	1576	4	0	0
T21	1582	6	0	0
T22	2712	0	0	0
T23	17212	0	0	0
T24	58043	0	0	0
T43	0	3	0	0
T65	1893	0	0	0
T66	3394	4	0	0
T98	1712	0	0	0
T144	0	2	0	0
T145	0	1	0	0
T146	0	6	0	0
T147	0	4	0	0
T148	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	468092615	165	0	0
CgEnOn_A	468092615	161	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	165	0	0
T3	68158	0	0	0
T19	4882	3	0	0
T20	1576	4	0	0
T21	1582	6	0	0
T22	2712	0	0	0
T23	17212	0	0	0
T24	58043	0	0	0
T43	0	3	0	0
T65	1893	0	0	0
T66	3394	4	0	0
T98	1712	0	0	0
T144	0	2	0	0
T145	0	1	0	0
T146	0	6	0	0
T147	0	4	0	0
T148	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	161	0	0
T3	68158	0	0	0
T19	4882	3	0	0
T20	1576	4	0	0
T21	1582	6	0	0
T22	2712	0	0	0
T23	17212	0	0	0
T24	58043	0	0	0
T43	0	3	0	0
T65	1893	0	0	0
T66	3394	4	0	0
T98	1712	0	0	0
T144	0	2	0	0
T145	0	1	0	0
T146	0	6	0	0
T147	0	4	0	0
T148	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Unreachable
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	224770963	157	0	0
CgEnOn_A	224770963	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224770963	157	0	0
T3	32716	0	0	0
T19	2357	5	0	0
T20	759	2	0	0
T21	798	3	0	0
T22	1301	0	0	0
T23	8262	0	0	0
T24	27861	0	0	0
T43	0	4	0	0
T65	908	0	0	0
T66	1673	4	0	0
T98	822	0	0	0
T144	0	2	0	0
T145	0	1	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224770963	156	0	0
T3	32716	0	0	0
T19	2357	5	0	0
T20	759	2	0	0
T21	798	3	0	0
T22	1301	0	0	0
T23	8262	0	0	0
T24	27861	0	0	0
T43	0	4	0	0
T65	908	0	0	0
T66	1673	4	0	0
T98	822	0	0	0
T144	0	2	0	0
T145	0	1	0	0
T146	0	4	0	0
T147	0	4	0	0
T148	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	109225953	7733	0	0
CgEnOn_A	109225953	5335	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109225953	7733	0	0
T1	191203	95	0	0
T2	128932	11	0	0
T4	694	1	0	0
T5	548	1	0	0
T6	2310	1	0	0
T16	1456	1	0	0
T17	2065	2	0	0
T18	762	1	0	0
T19	1151	5	0	0
T20	357	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	109225953	5335	0	0
T1	191203	90	0	0
T2	128932	6	0	0
T3	0	9	0	0
T9	0	29	0	0
T16	1456	0	0	0
T17	2065	1	0	0
T18	762	0	0	0
T19	1151	4	0	0
T20	357	1	0	0
T21	357	6	0	0
T22	725	0	0	0
T23	4817	0	0	0
T66	0	4	0	0
T99	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	218453085	7781	0	0
CgEnOn_A	218453085	5383	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218453085	7781	0	0
T1	382407	94	0	0
T2	257866	12	0	0
T4	1388	1	0	0
T5	1098	1	0	0
T6	4621	1	0	0
T16	2913	1	0	0
T17	4130	2	0	0
T18	1525	1	0	0
T19	2301	5	0	0
T20	714	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	218453085	5383	0	0
T1	382407	89	0	0
T2	257866	7	0	0
T3	0	9	0	0
T9	0	30	0	0
T16	2913	0	0	0
T17	4130	1	0	0
T18	1525	0	0	0
T19	2301	4	0	0
T20	714	1	0	0
T21	713	6	0	0
T22	1454	0	0	0
T23	9636	0	0	0
T66	0	4	0	0
T99	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	438700817	7811	0	0
CgEnOn_A	438700817	5407	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438700817	7811	0	0
T1	764386	91	0	0
T2	508696	13	0	0
T4	2868	1	0	0
T5	2023	1	0	0
T6	8006	1	0	0
T16	5386	1	0	0
T17	8381	2	0	0
T18	3129	1	0	0
T19	4737	5	0	0
T20	1467	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	438700817	5407	0	0
T1	764386	86	0	0
T2	508696	8	0	0
T3	0	10	0	0
T9	0	28	0	0
T16	5386	0	0	0
T17	8381	1	0	0
T18	3129	0	0	0
T19	4737	4	0	0
T20	1467	1	0	0
T21	1547	6	0	0
T22	2604	0	0	0
T23	16524	0	0	0
T66	0	4	0	0
T99	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	224770963	7816	0	0
CgEnOn_A	224770963	5410	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224770963	7816	0	0
T1	386531	91	0	0
T2	280281	12	0	0
T4	1434	1	0	0
T5	1012	1	0	0
T6	4003	1	0	0
T16	2693	1	0	0
T17	4190	2	0	0
T18	1564	1	0	0
T19	2357	6	0	0
T20	759	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224770963	5410	0	0
T1	386531	86	0	0
T2	280281	7	0	0
T3	0	10	0	0
T9	0	29	0	0
T16	2693	0	0	0
T17	4190	1	0	0
T18	1564	0	0	0
T19	2357	5	0	0
T20	759	2	0	0
T21	798	3	0	0
T22	1301	0	0	0
T23	8262	0	0	0
T66	0	4	0	0
T99	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	468092615	4094	0	0
CgEnOn_A	468092615	4090	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	4094	0	0
T1	802861	30	0	0
T2	589910	28	0	0
T4	2988	8	0	0
T5	2108	0	0	0
T6	8340	0	0	0
T9	0	10	0	0
T16	5611	0	0	0
T17	8730	1	0	0
T18	3258	5	0	0
T19	4882	3	0	0
T20	1576	4	0	0
T21	0	6	0	0
T66	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	4090	0	0
T1	802861	30	0	0
T2	589910	28	0	0
T4	2988	8	0	0
T5	2108	0	0	0
T6	8340	0	0	0
T9	0	10	0	0
T16	5611	0	0	0
T17	8730	1	0	0
T18	3258	5	0	0
T19	4882	3	0	0
T20	1576	4	0	0
T21	0	6	0	0
T66	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	468092615	4128	0	0
CgEnOn_A	468092615	4124	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	4128	0	0
T1	802861	34	0	0
T2	589910	28	0	0
T3	0	1	0	0
T4	2988	10	0	0
T5	2108	0	0	0
T6	8340	0	0	0
T16	5611	0	0	0
T17	8730	1	0	0
T18	3258	9	0	0
T19	4882	3	0	0
T20	1576	4	0	0
T21	0	6	0	0
T66	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	4124	0	0
T1	802861	34	0	0
T2	589910	28	0	0
T3	0	1	0	0
T4	2988	10	0	0
T5	2108	0	0	0
T6	8340	0	0	0
T16	5611	0	0	0
T17	8730	1	0	0
T18	3258	9	0	0
T19	4882	3	0	0
T20	1576	4	0	0
T21	0	6	0	0
T66	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	468092615	4049	0	0
CgEnOn_A	468092615	4045	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	4049	0	0
T1	802861	32	0	0
T2	589910	28	0	0
T3	0	1	0	0
T4	2988	9	0	0
T5	2108	0	0	0
T6	8340	0	0	0
T16	5611	0	0	0
T17	8730	1	0	0
T18	3258	11	0	0
T19	4882	3	0	0
T20	1576	4	0	0
T21	0	6	0	0
T66	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	4045	0	0
T1	802861	32	0	0
T2	589910	28	0	0
T3	0	1	0	0
T4	2988	9	0	0
T5	2108	0	0	0
T6	8340	0	0	0
T16	5611	0	0	0
T17	8730	1	0	0
T18	3258	11	0	0
T19	4882	3	0	0
T20	1576	4	0	0
T21	0	6	0	0
T66	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T19
1	0	Covered	T4,T1,T2
1	1	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	468092615	4086	0	0
CgEnOn_A	468092615	4082	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	4086	0	0
T1	802861	31	0	0
T2	589910	21	0	0
T3	0	1	0	0
T4	2988	7	0	0
T5	2108	0	0	0
T6	8340	0	0	0
T16	5611	0	0	0
T17	8730	1	0	0
T18	3258	8	0	0
T19	4882	3	0	0
T20	1576	4	0	0
T21	0	6	0	0
T66	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468092615	4082	0	0
T1	802861	31	0	0
T2	589910	21	0	0
T3	0	1	0	0
T4	2988	7	0	0
T5	2108	0	0	0
T6	8340	0	0	0
T16	5611	0	0	0
T17	8730	1	0	0
T18	3258	8	0	0
T19	4882	3	0	0
T20	1576	4	0	0
T21	0	6	0	0
T66	0	4	0	0