Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289693684

1

T5

3564

T6

2706

T7

2736

auto[1]

385012

1

T7

70

T24

608

T27

852

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289701542

1

T5

3564

T6

2706

T7

2708

auto[1]

377154

1

T7

98

T24

392

T27

562

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289585346

1

T5

3564

T6

2706

T7

2708

auto[1]

493350

1

T7

98

T24

434

T27

612

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

272327504

1

T5

3564

T6

2706

T7

2806

auto[1]

17751192

1

T24

2688

T27

1208

T17

2166

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

179504562

1

T5

3540

T6

1992

T7

2806

auto[1]

110574134

1

T5

24

T6

714

T24

306

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

163033576

1

T5

3540

T6

1992

T7

2708

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

108947624

1

T5

24

T6

714

T24

96

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

28258

1

T24

112

T27

114

T17

126

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6960

1

T18

14

T122

10

T3

148

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

15893808

1

T24

2340

T27

556

T17

1654

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1522972

1

T24

108

T27

84

T17

158

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

46552

1

T24

22

T27

80

T17

24

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

11384

1

T3

44

T11

56

T112

20

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

46050

1

T24

14

T27

2

T17

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1298

1

T11

48

T12

20

T181

18

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

10850

1

T24

78

T27

66

T17

48

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2422

1

T12

56

T181

68

T41

56

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

9158

1

T24

46

T27

2

T3

40

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2558

1

T3

42

T12

22

T13

34

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

18562

1

T24

72

T27

64

T3

178

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3314

1

T3

60

T12

104

T182

62

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

66576

1

T24

22

T18

94

T19

30

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3798

1

T19

6

T12

24

T181

34

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

30942

1

T24

130

T18

456

T19

44

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7428

1

T19

48

T12

200

T183

60

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

27758

1

T24

20

T27

6

T17

8

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6534

1

T24

12

T19

20

T3

38

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

54530

1

T27

178

T18

54

T20

76

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12842

1

T24

68

T19

40

T3

144

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

77592

1

T7

28

T24

34

T27

30

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6268

1

T24

22

T27

8

T18

30

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

46090

1

T7

70

T24

126

T27

108

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11772

1

T27

44

T18

150

T19

50

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

38822

1

T27

36

T17

40

T122

10

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9292

1

T27

4

T17

60

T3

62

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

75438

1

T27

156

T17

222

T122

50

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

17668

1

T27

42

T3

130

T11

224