Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	629985	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3590770

1

T4

2

T5

2

T1

246

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1033051	1			T4	4		T5	3		T1	57
values[0x0]	1464187	1			T4	3		T5	6		T1	216
values[0x1]	1723517	1			T4	4		T5	1		T1	227

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	346854	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3873901

1

T4

3

T5

4

T1

316

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16404	1			T1	2		T14	1		T22	16
valid_sources[0x01]	16796	1			T16	1		T18	1		T2	2
valid_sources[0x02]	16598	1			T16	2		T2	1		T3	5
valid_sources[0x03]	16737	1			T1	3		T16	1		T2	2
valid_sources[0x04]	17667	1			T16	1		T2	4		T22	2
valid_sources[0x05]	17064	1			T1	1		T2	1		T22	3
valid_sources[0x06]	15332	1			T1	1		T2	5		T22	6
valid_sources[0x07]	16378	1			T1	4		T14	1		T22	3
valid_sources[0x08]	16186	1			T1	1		T13	1		T16	1
valid_sources[0x09]	17393	1			T13	1		T18	4		T2	1
valid_sources[0x0a]	15344	1			T1	5		T18	2		T2	2
valid_sources[0x0b]	16349	1			T1	1		T16	1		T2	3
valid_sources[0x0c]	16170	1			T1	1		T16	1		T2	3
valid_sources[0x0d]	15438	1			T5	10		T2	1		T90	3
valid_sources[0x0e]	16746	1			T1	5		T16	1		T2	1
valid_sources[0x0f]	16428	1			T1	3		T13	2		T2	3
valid_sources[0x10]	16187	1			T1	3		T16	2		T2	4
valid_sources[0x11]	17465	1			T2	4		T22	2		T73	1
valid_sources[0x12]	15615	1			T1	5		T2	2		T22	5
valid_sources[0x13]	16581	1			T16	1		T2	4		T3	8
valid_sources[0x14]	16311	1			T3	1		T6	3		T88	1
valid_sources[0x15]	16232	1			T1	6		T2	1		T22	4
valid_sources[0x16]	16425	1			T1	5		T14	2		T2	2
valid_sources[0x17]	16193	1			T1	3		T13	2		T16	2
valid_sources[0x18]	16977	1			T1	4		T16	1		T2	2
valid_sources[0x19]	17027	1			T16	1		T2	5		T22	7
valid_sources[0x1a]	16236	1			T1	4		T13	1		T18	1
valid_sources[0x1b]	16275	1			T1	5		T2	3		T87	1
valid_sources[0x1c]	16683	1			T14	1		T18	2		T2	3
valid_sources[0x1d]	15782	1			T1	2		T18	3		T2	1
valid_sources[0x1e]	17125	1			T1	6		T16	1		T2	2
valid_sources[0x1f]	17767	1			T1	3		T14	2		T16	1
valid_sources[0x20]	16852	1			T1	1		T14	2		T2	2
valid_sources[0x21]	16399	1			T2	3		T6	5		T29	3
valid_sources[0x22]	15758	1			T1	1		T2	1		T22	1
valid_sources[0x23]	15743	1			T2	1		T22	2		T6	3
valid_sources[0x24]	15841	1			T1	6		T2	2		T19	184
valid_sources[0x25]	16603	1			T1	18		T16	1		T2	2
valid_sources[0x26]	16863	1			T2	4		T22	6		T86	1
valid_sources[0x27]	15892	1			T2	4		T22	2		T87	1
valid_sources[0x28]	17924	1			T1	4		T2	1		T22	5
valid_sources[0x29]	16060	1			T17	7		T2	3		T71	1
valid_sources[0x2a]	15967	1			T13	1		T14	2		T22	3
valid_sources[0x2b]	16505	1			T2	3		T22	5		T6	3
valid_sources[0x2c]	17472	1			T1	2		T14	1		T16	1
valid_sources[0x2d]	16534	1			T1	2		T18	1		T2	3
valid_sources[0x2e]	17001	1			T16	1		T2	3		T22	3
valid_sources[0x2f]	17080	1			T2	2		T22	2		T73	1
valid_sources[0x30]	16474	1			T2	2		T22	2		T25	1
valid_sources[0x31]	15677	1			T1	1		T16	2		T6	4
valid_sources[0x32]	16872	1			T2	3		T6	3		T89	3
valid_sources[0x33]	16963	1			T1	8		T13	1		T14	1
valid_sources[0x34]	17098	1			T14	1		T2	1		T6	2
valid_sources[0x35]	17427	1			T2	2		T3	6		T6	6
valid_sources[0x36]	16087	1			T1	2		T14	2		T2	2
valid_sources[0x37]	16457	1			T13	1		T14	2		T6	1
valid_sources[0x38]	16446	1			T14	3		T16	1		T2	2
valid_sources[0x39]	15904	1			T1	2		T2	4		T6	5
valid_sources[0x3a]	16530	1			T1	1		T2	2		T22	1
valid_sources[0x3b]	14748	1			T16	1		T22	5		T6	4
valid_sources[0x3c]	16782	1			T2	1		T22	2		T88	1
valid_sources[0x3d]	19660	1			T1	7		T14	3		T2	1
valid_sources[0x3e]	16515	1			T14	1		T16	1		T2	3
valid_sources[0x3f]	15709	1			T18	3		T2	3		T22	5
valid_sources[0x40]	16878	1			T14	1		T2	2		T22	3
valid_sources[0x41]	16159	1			T16	1		T2	7		T22	1
valid_sources[0x42]	16495	1			T16	2		T2	1		T22	5
valid_sources[0x43]	17998	1			T1	2		T13	1		T16	1
valid_sources[0x44]	17660	1			T1	4		T16	1		T2	3
valid_sources[0x45]	16377	1			T1	2		T16	1		T2	2
valid_sources[0x46]	15741	1			T1	4		T14	1		T16	1
valid_sources[0x47]	15119	1			T14	1		T2	4		T22	6
valid_sources[0x48]	16917	1			T1	1		T2	1		T22	11
valid_sources[0x49]	17703	1			T2	1		T22	3		T6	3
valid_sources[0x4a]	16365	1			T2	5		T22	3		T73	1
valid_sources[0x4b]	17744	1			T1	3		T2	3		T22	1
valid_sources[0x4c]	15464	1			T1	3		T2	2		T22	8
valid_sources[0x4d]	17302	1			T14	1		T16	1		T2	3
valid_sources[0x4e]	16313	1			T1	2		T13	1		T2	2
valid_sources[0x4f]	15456	1			T1	2		T2	2		T22	6
valid_sources[0x50]	16609	1			T1	2		T13	1		T14	2
valid_sources[0x51]	17365	1			T1	4		T2	3		T22	1
valid_sources[0x52]	16827	1			T16	1		T2	1		T22	4
valid_sources[0x53]	16658	1			T16	2		T2	3		T22	12
valid_sources[0x54]	17455	1			T2	5		T22	1		T6	2
valid_sources[0x55]	16429	1			T73	1		T6	2		T25	2
valid_sources[0x56]	16393	1			T16	1		T2	2		T73	2
valid_sources[0x57]	15567	1			T1	1		T16	3		T22	4
valid_sources[0x58]	16756	1			T1	1		T14	1		T2	1
valid_sources[0x59]	16766	1			T2	2		T22	4		T73	1
valid_sources[0x5a]	16003	1			T16	3		T2	2		T22	9
valid_sources[0x5b]	16179	1			T22	7		T25	1		T29	1
valid_sources[0x5c]	17144	1			T16	3		T2	1		T22	3
valid_sources[0x5d]	15595	1			T2	1		T22	9		T6	6
valid_sources[0x5e]	16576	1			T14	1		T2	5		T22	3
valid_sources[0x5f]	16819	1			T14	1		T16	1		T2	3
valid_sources[0x60]	15837	1			T1	1		T2	2		T3	5
valid_sources[0x61]	16968	1			T1	1		T13	1		T16	1
valid_sources[0x62]	15399	1			T1	2		T2	1		T22	3
valid_sources[0x63]	15243	1			T2	1		T22	4		T73	1
valid_sources[0x64]	17425	1			T13	1		T14	1		T2	2
valid_sources[0x65]	15486	1			T2	1		T22	8		T6	4
valid_sources[0x66]	16313	1			T18	2		T2	2		T22	2
valid_sources[0x67]	18823	1			T1	11		T14	1		T16	1
valid_sources[0x68]	15846	1			T2	4		T22	10		T86	1
valid_sources[0x69]	17415	1			T1	5		T16	1		T2	5
valid_sources[0x6a]	16548	1			T16	5		T2	1		T22	1
valid_sources[0x6b]	18095	1			T16	1		T2	1		T22	3
valid_sources[0x6c]	18214	1			T2	2		T22	6		T6	4
valid_sources[0x6d]	15626	1			T2	3		T22	4		T71	23
valid_sources[0x6e]	15484	1			T1	7		T2	3		T6	4
valid_sources[0x6f]	16915	1			T1	3		T2	2		T22	3
valid_sources[0x70]	15094	1			T1	2		T16	1		T2	2
valid_sources[0x71]	15222	1			T14	1		T18	1		T2	2
valid_sources[0x72]	16385	1			T1	1		T14	1		T2	2
valid_sources[0x73]	16383	1			T1	10		T18	3		T2	1
valid_sources[0x74]	16872	1			T1	2		T2	3		T6	1
valid_sources[0x75]	15925	1			T2	3		T22	1		T73	1
valid_sources[0x76]	15879	1			T2	1		T6	3		T25	1
valid_sources[0x77]	16019	1			T1	1		T2	3		T3	4
valid_sources[0x78]	15935	1			T2	2		T22	4		T73	1
valid_sources[0x79]	17757	1			T1	9		T2	3		T72	2
valid_sources[0x7a]	15410	1			T2	3		T22	4		T6	2
valid_sources[0x7b]	15817	1			T1	4		T16	1		T2	2
valid_sources[0x7c]	16244	1			T2	3		T22	2		T6	3
valid_sources[0x7d]	15973	1			T14	1		T2	4		T6	2
valid_sources[0x7e]	16044	1			T1	3		T2	2		T22	11
valid_sources[0x7f]	16526	1			T1	13		T16	1		T2	1
valid_sources[0x80]	17434	1			T1	4		T16	1		T2	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

904175

1

T4

1

T5

1

T1

30

values[0x0]

all_enables

biggest_size

1367560

1

T4

1

T5

1

T1

129

values[0x1]

all_enables

biggest_size

1319035

1

T1

87

T13

4

T14

5