Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T22
0	1	Covered	T2,T70,T6
1	0	Covered	T4,T5,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T22
1	0	Covered	T33,T34,T35
1	1	Covered	T4,T5,T1

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1206231825	13419	0	0
GateOpen_A	1206231825	20247	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1206231825	13419	0	0
T2	535038	23	0	0
T3	146579	0	0	0
T6	0	55	0	0
T14	8302	4	0	0
T15	7899	0	0	0
T16	6598	0	0	0
T17	3099	0	0	0
T18	7665	0	0	0
T19	199065	0	0	0
T22	279532	0	0	0
T33	0	4	0	0
T34	0	6	0	0
T35	0	14	0	0
T37	0	4	0	0
T70	7664	4	0	0
T166	0	35	0	0
T167	0	39	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1206231825	20247	0	0
T1	538909	0	0	0
T2	535038	31	0	0
T4	11028	4	0	0
T5	2835	0	0	0
T13	8943	0	0	0
T14	8302	4	0	0
T15	7899	0	0	0
T16	6598	0	0	0
T17	3099	0	0	0
T18	7665	4	0	0
T22	0	76	0	0
T23	0	4	0	0
T36	0	4	0	0
T70	0	8	0	0
T71	0	4	0	0
T73	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T22
0	1	Covered	T2,T70,T6
1	0	Covered	T4,T5,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T22
1	0	Covered	T33,T34,T35
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	133149827	3182	0	0
GateOpen_A	133149827	4886	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133149827	3182	0	0
T2	59990	5	0	0
T3	16283	0	0	0
T6	0	10	0	0
T14	914	1	0	0
T15	869	0	0	0
T16	729	0	0	0
T17	332	0	0	0
T18	1121	0	0	0
T19	22103	0	0	0
T22	20562	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	0	1	0	0
T70	843	1	0	0
T166	0	10	0	0
T167	0	6	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133149827	4886	0	0
T1	59870	0	0	0
T2	59990	7	0	0
T4	1286	1	0	0
T5	311	0	0	0
T13	985	0	0	0
T14	914	1	0	0
T15	869	0	0	0
T16	729	0	0	0
T17	332	0	0	0
T18	1121	1	0	0
T22	0	19	0	0
T23	0	1	0	0
T36	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T73	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T22
0	1	Covered	T2,T70,T6
1	0	Covered	T4,T5,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T22
1	0	Covered	T33,T34,T35
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	266300470	3427	0	0
GateOpen_A	266300470	5131	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266300470	3427	0	0
T2	119981	6	0	0
T3	32565	0	0	0
T6	0	15	0	0
T14	1828	1	0	0
T15	1738	0	0	0
T16	1458	0	0	0
T17	664	0	0	0
T18	2246	0	0	0
T19	44205	0	0	0
T22	41117	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	0	1	0	0
T70	1686	1	0	0
T166	0	8	0	0
T167	0	13	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266300470	5131	0	0
T1	119739	0	0	0
T2	119981	8	0	0
T4	2571	1	0	0
T5	622	0	0	0
T13	1970	0	0	0
T14	1828	1	0	0
T15	1738	0	0	0
T16	1458	0	0	0
T17	664	0	0	0
T18	2246	1	0	0
T22	0	19	0	0
T23	0	1	0	0
T36	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T73	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T22
0	1	Covered	T2,T70,T6
1	0	Covered	T4,T5,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T22
1	0	Covered	T33,T34,T35
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	534026706	3431	0	0
GateOpen_A	534026706	5141	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534026706	3431	0	0
T2	236708	7	0	0
T3	65153	0	0	0
T6	0	16	0	0
T14	3707	1	0	0
T15	3528	0	0	0
T16	2940	0	0	0
T17	1402	0	0	0
T18	2865	0	0	0
T19	88503	0	0	0
T22	145233	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	0	1	0	0
T70	3423	1	0	0
T166	0	9	0	0
T167	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534026706	5141	0	0
T1	239530	0	0	0
T2	236708	9	0	0
T4	4781	1	0	0
T5	1268	0	0	0
T13	3992	0	0	0
T14	3707	1	0	0
T15	3528	0	0	0
T16	2940	0	0	0
T17	1402	0	0	0
T18	2865	1	0	0
T22	0	19	0	0
T23	0	1	0	0
T36	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T73	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T22
0	1	Covered	T2,T70,T6
1	0	Covered	T4,T5,T1

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T22
1	0	Covered	T33,T34,T35
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	272754822	3379	0	0
GateOpen_A	272754822	5089	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272754822	3379	0	0
T2	118359	5	0	0
T3	32578	0	0	0
T6	0	14	0	0
T14	1853	1	0	0
T15	1764	0	0	0
T16	1471	0	0	0
T17	701	0	0	0
T18	1433	0	0	0
T19	44254	0	0	0
T22	72620	0	0	0
T33	0	1	0	0
T34	0	3	0	0
T35	0	5	0	0
T37	0	1	0	0
T70	1712	1	0	0
T166	0	8	0	0
T167	0	10	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272754822	5089	0	0
T1	119770	0	0	0
T2	118359	7	0	0
T4	2390	1	0	0
T5	634	0	0	0
T13	1996	0	0	0
T14	1853	1	0	0
T15	1764	0	0	0
T16	1471	0	0	0
T17	701	0	0	0
T18	1433	1	0	0
T22	0	19	0	0
T23	0	1	0	0
T36	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T73	0	1	0	0