Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	796817190	78052	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	796817190	78052	0	0
T1	299415	243	0	0
T2	197260	83	0	0
T3	166280	56	0	0
T6	0	55	0	0
T7	0	43	0	0
T8	0	1629	0	0
T9	0	89	0	0
T10	0	1949	0	0
T11	0	132	0	0
T12	0	195	0	0
T13	4985	0	0	0
T14	9265	0	0	0
T15	18370	0	0	0
T16	12715	0	0	0
T17	7005	0	0	0
T18	11035	0	0	0
T19	456360	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159363438	11736	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	11736	0	0
T1	59883	39	0	0
T2	39452	14	0	0
T3	33256	8	0	0
T6	0	9	0	0
T7	0	7	0	0
T8	0	246	0	0
T9	0	13	0	0
T10	0	346	0	0
T11	0	21	0	0
T12	0	29	0	0
T13	997	0	0	0
T14	1853	0	0	0
T15	3674	0	0	0
T16	2543	0	0	0
T17	1401	0	0	0
T18	2207	0	0	0
T19	91272	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159363438	11526	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	11526	0	0
T1	59883	39	0	0
T2	39452	14	0	0
T3	33256	8	0	0
T6	0	9	0	0
T7	0	7	0	0
T8	0	244	0	0
T9	0	11	0	0
T10	0	346	0	0
T11	0	20	0	0
T12	0	25	0	0
T13	997	0	0	0
T14	1853	0	0	0
T15	3674	0	0	0
T16	2543	0	0	0
T17	1401	0	0	0
T18	2207	0	0	0
T19	91272	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159363438	15701	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	15701	0	0
T1	59883	49	0	0
T2	39452	17	0	0
T3	33256	11	0	0
T6	0	11	0	0
T7	0	9	0	0
T8	0	328	0	0
T9	0	17	0	0
T10	0	384	0	0
T11	0	27	0	0
T12	0	38	0	0
T13	997	0	0	0
T14	1853	0	0	0
T15	3674	0	0	0
T16	2543	0	0	0
T17	1401	0	0	0
T18	2207	0	0	0
T19	91272	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159363438	15643	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	15643	0	0
T1	59883	49	0	0
T2	39452	17	0	0
T3	33256	11	0	0
T6	0	11	0	0
T7	0	9	0	0
T8	0	324	0	0
T9	0	19	0	0
T10	0	390	0	0
T11	0	27	0	0
T12	0	41	0	0
T13	997	0	0	0
T14	1853	0	0	0
T15	3674	0	0	0
T16	2543	0	0	0
T17	1401	0	0	0
T18	2207	0	0	0
T19	91272	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	159363438	23446	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	23446	0	0
T1	59883	67	0	0
T2	39452	21	0	0
T3	33256	18	0	0
T6	0	15	0	0
T7	0	11	0	0
T8	0	487	0	0
T9	0	29	0	0
T10	0	483	0	0
T11	0	37	0	0
T12	0	62	0	0
T13	997	0	0	0
T14	1853	0	0	0
T15	3674	0	0	0
T16	2543	0	0	0
T17	1401	0	0	0
T18	2207	0	0	0
T19	91272	0	0	0