Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T1
0	1	Unreachable
1	0	Covered	T2,T22,T6

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	159363438	156723223	0	0
AllClkBypReqTrue_A	159363438	130399	0	0
IoClkBypReqFalse_A	159363438	156638599	0	2415
IoClkBypReqTrue_A	159363438	210311	0	0
LcClkBypAckFalse_A	159363438	156729385	0	0
LcClkBypAckTrue_A	159363438	124237	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	156723223	0	0
T1	59883	59849	0	0
T2	39452	39046	0	0
T4	995	927	0	0
T5	1294	1106	0	0
T13	997	969	0	0
T14	1853	1792	0	0
T15	3674	3475	0	0
T16	2543	2437	0	0
T17	1401	1210	0	0
T18	2207	1909	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	130399	0	0
T1	59883	0	0	0
T2	39452	329	0	0
T4	995	34	0	0
T5	1294	8	0	0
T6	0	313	0	0
T13	997	0	0	0
T14	1853	0	0	0
T15	3674	0	0	0
T16	2543	0	0	0
T17	1401	0	0	0
T18	2207	225	0	0
T72	0	8	0	0
T73	0	209	0	0
T86	0	35	0	0
T87	0	96	0	0
T88	0	154	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	156638599	0	2415
T1	59883	59847	0	3
T2	39452	38592	0	3
T4	995	864	0	3
T5	1294	1112	0	3
T13	997	967	0	3
T14	1853	1790	0	3
T15	3674	3473	0	3
T16	2543	2435	0	3
T17	1401	1146	0	3
T18	2207	1802	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	210311	0	0
T1	59883	0	0	0
T2	39452	777	0	0
T4	995	95	0	0
T5	1294	0	0	0
T6	0	541	0	0
T13	997	0	0	0
T14	1853	0	0	0
T15	3674	0	0	0
T16	2543	0	0	0
T17	1401	62	0	0
T18	2207	330	0	0
T36	0	243	0	0
T86	0	76	0	0
T87	0	160	0	0
T88	0	428	0	0
T90	0	99	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	156729385	0	0
T1	59883	59849	0	0
T2	39452	38884	0	0
T4	995	874	0	0
T5	1294	1114	0	0
T13	997	969	0	0
T14	1853	1792	0	0
T15	3674	3475	0	0
T16	2543	2437	0	0
T17	1401	1191	0	0
T18	2207	1928	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	124237	0	0
T1	59883	0	0	0
T2	39452	491	0	0
T4	995	87	0	0
T5	1294	0	0	0
T6	0	356	0	0
T13	997	0	0	0
T14	1853	0	0	0
T15	3674	0	0	0
T16	2543	0	0	0
T17	1401	19	0	0
T18	2207	206	0	0
T36	0	77	0	0
T86	0	879	0	0
T87	0	78	0	0
T88	0	224	0	0
T90	0	61	0	0