Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2147483647	15267	0	0
TransStop_A	2147483647	7788	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15267	0	0
T2	986316	26	0	0
T3	271480	0	0	0
T6	0	106	0	0
T8	0	92	0	0
T14	15448	4	0	0
T15	14700	42	0	0
T16	12256	41	0	0
T17	5840	0	0	0
T18	11936	0	0	0
T19	368772	0	0	0
T22	605156	0	0	0
T25	0	4	0	0
T37	0	4	0	0
T70	14264	0	0	0
T71	0	16	0	0
T113	0	32	0	0
T114	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	7788	0	0
T2	986316	11	0	0
T3	271480	0	0	0
T6	0	54	0	0
T8	0	207	0	0
T9	0	21	0	0
T14	15448	4	0	0
T15	14700	22	0	0
T16	12256	18	0	0
T17	5840	0	0	0
T18	11936	0	0	0
T19	368772	0	0	0
T22	605156	0	0	0
T37	0	4	0	0
T67	0	2	0	0
T70	14264	0	0	0
T71	0	4	0	0
T113	0	15	0	0
T114	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	568507384	3800	0	0
TransStop_A	568507384	1951	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568507384	3800	0	0
T2	246579	6	0	0
T3	67870	0	0	0
T6	0	23	0	0
T14	3862	1	0	0
T15	3675	11	0	0
T16	3064	10	0	0
T17	1460	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T25	0	1	0	0
T37	0	1	0	0
T70	3566	0	0	0
T71	0	3	0	0
T113	0	10	0	0
T114	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568507384	1951	0	0
T2	246579	2	0	0
T3	67870	0	0	0
T6	0	13	0	0
T8	0	56	0	0
T9	0	6	0	0
T14	3862	1	0	0
T15	3675	4	0	0
T16	3064	4	0	0
T17	1460	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T37	0	1	0	0
T67	0	1	0	0
T70	3566	0	0	0
T113	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	568507384	3791	0	0
TransStop_A	568507384	1954	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568507384	3791	0	0
T2	246579	4	0	0
T3	67870	0	0	0
T6	0	22	0	0
T14	3862	1	0	0
T15	3675	9	0	0
T16	3064	10	0	0
T17	1460	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T25	0	1	0	0
T37	0	1	0	0
T70	3566	0	0	0
T71	0	2	0	0
T113	0	8	0	0
T114	0	2	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568507384	1954	0	0
T2	246579	0	0	0
T3	67870	0	0	0
T6	0	12	0	0
T8	0	61	0	0
T9	0	4	0	0
T14	3862	1	0	0
T15	3675	5	0	0
T16	3064	5	0	0
T17	1460	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T37	0	1	0	0
T67	0	1	0	0
T70	3566	0	0	0
T113	0	3	0	0
T114	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	568507384	3822	0	0
TransStop_A	568507384	1925	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568507384	3822	0	0
T2	246579	10	0	0
T3	67870	0	0	0
T6	0	33	0	0
T8	0	92	0	0
T14	3862	1	0	0
T15	3675	8	0	0
T16	3064	11	0	0
T17	1460	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T25	0	1	0	0
T37	0	1	0	0
T70	3566	0	0	0
T71	0	5	0	0
T113	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568507384	1925	0	0
T2	246579	5	0	0
T3	67870	0	0	0
T6	0	15	0	0
T8	0	43	0	0
T9	0	6	0	0
T14	3862	1	0	0
T15	3675	5	0	0
T16	3064	5	0	0
T17	1460	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T37	0	1	0	0
T70	3566	0	0	0
T71	0	2	0	0
T113	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	568507384	3854	0	0
TransStop_A	568507384	1958	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568507384	3854	0	0
T2	246579	6	0	0
T3	67870	0	0	0
T6	0	28	0	0
T14	3862	1	0	0
T15	3675	14	0	0
T16	3064	10	0	0
T17	1460	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T25	0	1	0	0
T37	0	1	0	0
T70	3566	0	0	0
T71	0	6	0	0
T113	0	10	0	0
T114	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568507384	1958	0	0
T2	246579	4	0	0
T3	67870	0	0	0
T6	0	14	0	0
T8	0	47	0	0
T9	0	5	0	0
T14	3862	1	0	0
T15	3675	8	0	0
T16	3064	4	0	0
T17	1460	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T37	0	1	0	0
T70	3566	0	0	0
T71	0	2	0	0
T113	0	5	0	0