Unified Coverage Report :: Module :: prim_mubi4_sender

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_clkmgr_byp.u_io_byp_req	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_all_byp_req	100.00	100.00					100.00
tb.dut.u_clkmgr_byp.u_hi_speed_sel	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_main_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_usb_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_infra	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_secure	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_main_secure	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_timers	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div4_peri	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_div2_peri	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_io_peri	100.00	100.00					100.00
tb.dut.u_prim_mubi4_sender_clk_usb_peri	100.00	100.00					100.00
tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender	100.00	100.00					100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00
gen_sec_buf.u_prim_sec_buf	100.00	100.00

---

Module Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_clkmgr_byp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_aes_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_hmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_kmac_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_clk_main_otbn_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=1,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_io_byp_req

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_all_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
85	1	1

---

Line Coverage for Module : prim_mubi4_sender ( parameter AsyncOn=1,EnSecBuf=0,ResetValue=6 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_hi_speed_sel

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_main_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_usb_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_main_secure

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_io_peri

SCORE	LINE
100.00	100.00

tb.dut.u_prim_mubi4_sender_clk_usb_peri

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	2147483647	2147483647	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2874311	2872802	0	0
T2	2787880	2783188	0	0
T4	57485	55722	0	0
T5	18096	15705	0	0
T13	47789	46606	0	0
T14	47153	45711	0	0
T15	50598	47970	0	0
T16	40659	39032	0	0
T17	19817	17303	0	0
T18	42091	40899	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_byp_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	159363438	156855978	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	156855978	0	0
T1	59883	59850	0	0
T2	39452	39378	0	0
T4	995	962	0	0
T5	1294	1115	0	0
T13	997	970	0	0
T14	1853	1793	0	0
T15	3674	3476	0	0
T16	2543	2438	0	0
T17	1401	1211	0	0
T18	2207	2135	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_byp_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	159363438	156855978	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	156855978	0	0
T1	59883	59850	0	0
T2	39452	39378	0	0
T4	995	962	0	0
T5	1294	1115	0	0
T13	997	970	0	0
T14	1853	1793	0	0
T15	3674	3476	0	0
T16	2543	2438	0	0
T17	1401	1211	0	0
T18	2207	2135	0	0

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_hi_speed_sel

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	159363438	156855978	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	156855978	0	0
T1	59883	59850	0	0
T2	39452	39378	0	0
T4	995	962	0	0
T5	1294	1115	0	0
T13	997	970	0	0
T14	1853	1793	0	0
T15	3674	3476	0	0
T16	2543	2438	0	0
T17	1401	1211	0	0
T18	2207	2135	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	133149421	132606750	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133149421	132606750	0	0
T1	59869	59848	0	0
T2	59989	59951	0	0
T4	1285	1264	0	0
T5	311	283	0	0
T13	985	971	0	0
T14	914	897	0	0
T15	869	834	0	0
T16	729	705	0	0
T17	332	308	0	0
T18	1120	1106	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	568506940	563957846	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	563957846	0	0
T1	249518	249378	0	0
T2	246579	246109	0	0
T4	4980	4811	0	0
T5	1321	1137	0	0
T13	4158	4046	0	0
T14	3861	3734	0	0
T15	3674	3476	0	0
T16	3063	2937	0	0
T17	1459	1262	0	0
T18	2984	2887	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	272754415	270565317	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272754415	270565317	0	0
T1	119770	119703	0	0
T2	118359	118135	0	0
T4	2390	2310	0	0
T5	633	545	0	0
T13	1995	1942	0	0
T14	1853	1793	0	0
T15	1763	1669	0	0
T16	1470	1409	0	0
T17	701	606	0	0
T18	1432	1385	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	534026253	529740496	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534026253	529740496	0	0
T1	239530	239395	0	0
T2	236707	236258	0	0
T4	4780	4618	0	0
T5	1268	1092	0	0
T13	3991	3884	0	0
T14	3706	3585	0	0
T15	3527	3337	0	0
T16	2940	2819	0	0
T17	1401	1211	0	0
T18	2865	2771	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	266300058	265214626	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266300058	265214626	0	0
T1	119739	119698	0	0
T2	119981	119905	0	0
T4	2570	2529	0	0
T5	621	566	0	0
T13	1969	1942	0	0
T14	1827	1792	0	0
T15	1738	1669	0	0
T16	1458	1410	0	0
T17	664	616	0	0
T18	2246	2218	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	133149421	132606750	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133149421	132606750	0	0
T1	59869	59848	0	0
T2	59989	59951	0	0
T4	1285	1264	0	0
T5	311	283	0	0
T13	985	971	0	0
T14	914	897	0	0
T15	869	834	0	0
T16	729	705	0	0
T17	332	308	0	0
T18	1120	1106	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	568506940	563957846	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	563957846	0	0
T1	249518	249378	0	0
T2	246579	246109	0	0
T4	4980	4811	0	0
T5	1321	1137	0	0
T13	4158	4046	0	0
T14	3861	3734	0	0
T15	3674	3476	0	0
T16	3063	2937	0	0
T17	1459	1262	0	0
T18	2984	2887	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	133149421	132606750	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133149421	132606750	0	0
T1	59869	59848	0	0
T2	59989	59951	0	0
T4	1285	1264	0	0
T5	311	283	0	0
T13	985	971	0	0
T14	914	897	0	0
T15	869	834	0	0
T16	729	705	0	0
T17	332	308	0	0
T18	1120	1106	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	133149421	132606750	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133149421	132606750	0	0
T1	59869	59848	0	0
T2	59989	59951	0	0
T4	1285	1264	0	0
T5	311	283	0	0
T13	985	971	0	0
T14	914	897	0	0
T15	869	834	0	0
T16	729	705	0	0
T17	332	308	0	0
T18	1120	1106	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	266300058	265214626	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266300058	265214626	0	0
T1	119739	119698	0	0
T2	119981	119905	0	0
T4	2570	2529	0	0
T5	621	566	0	0
T13	1969	1942	0	0
T14	1827	1792	0	0
T15	1738	1669	0	0
T16	1458	1410	0	0
T17	664	616	0	0
T18	2246	2218	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	534026253	529740496	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534026253	529740496	0	0
T1	239530	239395	0	0
T2	236707	236258	0	0
T4	4780	4618	0	0
T5	1268	1092	0	0
T13	3991	3884	0	0
T14	3706	3585	0	0
T15	3527	3337	0	0
T16	2940	2819	0	0
T17	1401	1211	0	0
T18	2865	2771	0	0

Line Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_mubi4_sender_clk_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	272754415	270565317	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272754415	270565317	0	0
T1	119770	119703	0	0
T2	118359	118135	0	0
T4	2390	2310	0	0
T5	633	545	0	0
T13	1995	1942	0	0
T14	1853	1793	0	0
T15	1763	1669	0	0
T16	1470	1409	0	0
T17	701	606	0	0
T18	1432	1385	0	0

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	568506940	563957846	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	563957846	0	0
T1	249518	249378	0	0
T2	246579	246109	0	0
T4	4980	4811	0	0
T5	1321	1137	0	0
T13	4158	4046	0	0
T14	3861	3734	0	0
T15	3674	3476	0	0
T16	3063	2937	0	0
T17	1459	1262	0	0
T18	2984	2887	0	0

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	568506940	563957846	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	563957846	0	0
T1	249518	249378	0	0
T2	246579	246109	0	0
T4	4980	4811	0	0
T5	1321	1137	0	0
T13	4158	4046	0	0
T14	3861	3734	0	0
T15	3674	3476	0	0
T16	3063	2937	0	0
T17	1459	1262	0	0
T18	2984	2887	0	0

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	568506940	563957846	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	563957846	0	0
T1	249518	249378	0	0
T2	246579	246109	0	0
T4	4980	4811	0	0
T5	1321	1137	0	0
T13	4158	4046	0	0
T14	3861	3734	0	0
T15	3674	3476	0	0
T16	3063	2937	0	0
T17	1459	1262	0	0
T18	2984	2887	0	0

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	34	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34	1	1
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	568506940	563957846	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	563957846	0	0
T1	249518	249378	0	0
T2	246579	246109	0	0
T4	4980	4811	0	0
T5	1321	1137	0	0
T13	4158	4046	0	0
T14	3861	3734	0	0
T15	3674	3476	0	0
T16	3063	2937	0	0
T17	1459	1262	0	0
T18	2984	2887	0	0