Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	160294252	5279885	0	0
clk_enables_rd_A	160294252	38355	0	0
clk_hints_rd_A	160294252	34563	0	0
extclk_ctrl_rd_A	160294252	42479	0	0
extclk_ctrl_regwen_rd_A	160294252	32135	0	0
jitter_enable_rd_A	160294252	49419	0	0
jitter_regwen_rd_A	160294252	36508	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160294252	5279885	0	0
T8	423610	146542	0	0
T9	203503	0	0	0
T10	228381	66812	0	0
T11	31512	0	0	0
T20	0	80658	0	0
T21	0	80518	0	0
T26	0	114765	0	0
T30	0	133580	0	0
T60	0	162609	0	0
T61	0	138171	0	0
T62	0	83154	0	0
T63	0	51371	0	0
T64	2425	0	0	0
T65	1651	0	0	0
T66	2119	0	0	0
T67	1378	0	0	0
T68	1932	0	0	0
T69	73429	0	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160294252	38355	0	0
T2	39452	0	0	0
T3	33256	0	0	0
T10	0	2896	0	0
T14	1853	1	0	0
T15	3674	0	0	0
T16	2543	0	0	0
T17	1401	0	0	0
T18	2207	0	0	0
T19	91272	0	0	0
T20	0	3043	0	0
T22	16642	0	0	0
T30	0	5428	0	0
T63	0	2050	0	0
T70	926	0	0	0
T135	0	19	0	0
T136	0	1	0	0
T137	0	7	0	0
T138	0	5	0	0
T139	0	3	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160294252	34563	0	0
T2	39452	0	0	0
T3	33256	0	0	0
T10	0	2546	0	0
T14	1853	4	0	0
T15	3674	0	0	0
T16	2543	0	0	0
T17	1401	0	0	0
T18	2207	0	0	0
T19	91272	0	0	0
T20	0	2602	0	0
T22	16642	0	0	0
T30	0	4511	0	0
T63	0	2060	0	0
T70	926	0	0	0
T135	0	17	0	0
T136	0	2	0	0
T138	0	6	0	0
T139	0	4	0	0
T140	0	1494	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160294252	42479	0	0
T2	39452	53	0	0
T3	33256	0	0	0
T10	0	3322	0	0
T19	91272	0	0	0
T20	0	3069	0	0
T22	16642	0	0	0
T23	9720	0	0	0
T36	1670	0	0	0
T64	0	54	0	0
T70	926	0	0	0
T71	2261	0	0	0
T72	743	0	0	0
T73	1655	0	0	0
T92	0	48	0	0
T135	0	83	0	0
T141	0	5	0	0
T142	0	42	0	0
T143	0	28	0	0
T144	0	6	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160294252	32135	0	0
T10	228381	2301	0	0
T11	31512	0	0	0
T12	226631	0	0	0
T20	0	2489	0	0
T30	0	4350	0	0
T63	0	1909	0	0
T68	1932	0	0	0
T69	73429	0	0	0
T74	41492	0	0	0
T111	0	54	0	0
T140	0	1246	0	0
T145	0	4	0	0
T146	0	23	0	0
T147	0	43	0	0
T148	0	26	0	0
T149	962	0	0	0
T150	1650	0	0	0
T151	1331	0	0	0
T152	909	0	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160294252	49419	0	0
T2	39452	0	0	0
T3	33256	0	0	0
T10	0	4183	0	0
T14	1853	138	0	0
T15	3674	0	0	0
T16	2543	0	0	0
T17	1401	0	0	0
T18	2207	0	0	0
T19	91272	0	0	0
T20	0	3768	0	0
T22	16642	0	0	0
T30	0	5842	0	0
T70	926	0	0	0
T135	0	561	0	0
T136	0	130	0	0
T137	0	97	0	0
T138	0	59	0	0
T139	0	114	0	0
T153	0	97	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	160294252	36508	0	0
T10	228381	2543	0	0
T11	31512	0	0	0
T12	226631	0	0	0
T20	0	3002	0	0
T30	0	5195	0	0
T63	0	2331	0	0
T68	1932	0	0	0
T69	73429	0	0	0
T74	41492	0	0	0
T140	0	1493	0	0
T149	962	0	0	0
T150	1650	0	0	0
T151	1331	0	0	0
T152	909	0	0	0
T154	0	3996	0	0
T155	0	1031	0	0
T156	0	3261	0	0
T157	0	623	0	0
T158	0	1985	0	0