Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	478090314	461	0	0
StatusRise_A	478090314	461	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478090314	461	0	0
T7	54501	0	0	0
T24	42564	0	0	0
T25	148413	0	0	0
T28	5232	0	0	0
T29	4857	0	0	0
T33	3336	3	0	0
T34	0	7	0	0
T35	0	13	0	0
T37	3285	0	0	0
T89	7896	0	0	0
T90	2736	0	0	0
T159	0	9	0	0
T160	0	15	0	0
T161	0	14	0	0
T162	0	9	0	0
T163	0	3	0	0
T164	0	7	0	0
T165	0	16	0	0
T166	2058	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	478090314	461	0	0
T7	54501	0	0	0
T24	42564	0	0	0
T25	148413	0	0	0
T28	5232	0	0	0
T29	4857	0	0	0
T33	3336	3	0	0
T34	0	7	0	0
T35	0	13	0	0
T37	3285	0	0	0
T89	7896	0	0	0
T90	2736	0	0	0
T159	0	9	0	0
T160	0	15	0	0
T161	0	14	0	0
T162	0	9	0	0
T163	0	3	0	0
T164	0	7	0	0
T165	0	16	0	0
T166	2058	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	159363438	153	0	0
StatusRise_A	159363438	153	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	153	0	0
T7	18167	0	0	0
T24	14188	0	0	0
T25	49471	0	0	0
T28	1744	0	0	0
T29	1619	0	0	0
T33	1112	1	0	0
T34	0	3	0	0
T35	0	5	0	0
T37	1095	0	0	0
T89	2632	0	0	0
T90	912	0	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	6	0	0
T166	686	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	153	0	0
T7	18167	0	0	0
T24	14188	0	0	0
T25	49471	0	0	0
T28	1744	0	0	0
T29	1619	0	0	0
T33	1112	1	0	0
T34	0	3	0	0
T35	0	5	0	0
T37	1095	0	0	0
T89	2632	0	0	0
T90	912	0	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	6	0	0
T166	686	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	159363438	156	0	0
StatusRise_A	159363438	156	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	156	0	0
T7	18167	0	0	0
T24	14188	0	0	0
T25	49471	0	0	0
T28	1744	0	0	0
T29	1619	0	0	0
T33	1112	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	1095	0	0	0
T89	2632	0	0	0
T90	912	0	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	4	0	0
T166	686	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	156	0	0
T7	18167	0	0	0
T24	14188	0	0	0
T25	49471	0	0	0
T28	1744	0	0	0
T29	1619	0	0	0
T33	1112	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	1095	0	0	0
T89	2632	0	0	0
T90	912	0	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	4	0	0
T166	686	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	159363438	152	0	0
StatusRise_A	159363438	152	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	152	0	0
T7	18167	0	0	0
T24	14188	0	0	0
T25	49471	0	0	0
T28	1744	0	0	0
T29	1619	0	0	0
T33	1112	1	0	0
T34	0	3	0	0
T35	0	5	0	0
T37	1095	0	0	0
T89	2632	0	0	0
T90	912	0	0	0
T159	0	2	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	6	0	0
T166	686	0	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	159363438	152	0	0
T7	18167	0	0	0
T24	14188	0	0	0
T25	49471	0	0	0
T28	1744	0	0	0
T29	1619	0	0	0
T33	1112	1	0	0
T34	0	3	0	0
T35	0	5	0	0
T37	1095	0	0	0
T89	2632	0	0	0
T90	912	0	0	0
T159	0	2	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	6	0	0
T166	686	0	0	0