Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47671	0	0
CgEnOn_A	2147483647	38254	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47671	0	0
T1	419138	3	0	0
T2	663256	40	0	0
T3	67869	0	0	0
T4	8635	3	0	0
T5	2200	3	0	0
T7	261476	0	0	0
T10	0	5	0	0
T13	6945	3	0	0
T14	10308	7	0	0
T15	9808	14	0	0
T16	8190	13	0	0
T17	3856	3	0	0
T18	9215	3	0	0
T24	93112	0	0	0
T25	376051	0	0	0
T28	3790	0	0	0
T29	3651	0	0	0
T33	3726	6	0	0
T34	0	8	0	0
T35	0	15	0	0
T37	5785	0	0	0
T61	0	5	0	0
T71	0	3	0	0
T89	6005	0	0	0
T90	12089	0	0	0
T159	0	15	0	0
T160	0	25	0	0
T161	0	25	0	0
T162	0	10	0	0
T163	0	5	0	0
T166	9105	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38254	0	0
T2	1521352	31	0	0
T3	418053	0	0	0
T6	0	85	0	0
T7	561852	0	0	0
T10	0	4	0	0
T14	23744	4	0	0
T15	22593	11	0	0
T16	18849	0	0	0
T17	8934	0	0	0
T18	19599	0	0	0
T19	567835	0	0	0
T22	884688	0	0	0
T24	233867	0	0	0
T25	816414	4	0	0
T28	8299	0	0	0
T29	7876	0	0	0
T33	8119	9	0	0
T34	0	11	0	0
T35	0	15	0	0
T37	12581	4	0	0
T61	0	4	0	0
T70	21921	8	0	0
T89	12805	0	0	0
T90	25399	0	0	0
T159	0	15	0	0
T160	0	25	0	0
T161	0	25	0	0
T162	0	10	0	0
T163	0	5	0	0
T164	0	3	0	0
T165	0	4	0	0
T166	19752	29	0	0
T167	0	47	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T6
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	266300058	164	0	0
CgEnOn_A	266300058	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266300058	164	0	0
T7	58082	0	0	0
T10	0	1	0	0
T24	15450	0	0	0
T25	83649	0	0	0
T28	819	0	0	0
T29	806	0	0	0
T33	819	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	1262	0	0	0
T61	0	1	0	0
T89	1351	0	0	0
T90	2775	0	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	1	0	0
T166	1993	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266300058	164	0	0
T7	58082	0	0	0
T10	0	1	0	0
T24	15450	0	0	0
T25	83649	0	0	0
T28	819	0	0	0
T29	806	0	0	0
T33	819	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	1262	0	0	0
T61	0	1	0	0
T89	1351	0	0	0
T90	2775	0	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	1	0	0
T166	1993	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T6
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	133149421	164	0	0
CgEnOn_A	133149421	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133149421	164	0	0
T7	29041	0	0	0
T10	0	1	0	0
T24	7726	0	0	0
T25	41825	0	0	0
T28	409	0	0	0
T29	403	0	0	0
T33	410	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	631	0	0	0
T61	0	1	0	0
T89	674	0	0	0
T90	1387	0	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	1	0	0
T166	997	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133149421	164	0	0
T7	29041	0	0	0
T10	0	1	0	0
T24	7726	0	0	0
T25	41825	0	0	0
T28	409	0	0	0
T29	403	0	0	0
T33	410	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	631	0	0	0
T61	0	1	0	0
T89	674	0	0	0
T90	1387	0	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	1	0	0
T166	997	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T6
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	133149421	164	0	0
CgEnOn_A	133149421	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133149421	164	0	0
T7	29041	0	0	0
T10	0	1	0	0
T24	7726	0	0	0
T25	41825	0	0	0
T28	409	0	0	0
T29	403	0	0	0
T33	410	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	631	0	0	0
T61	0	1	0	0
T89	674	0	0	0
T90	1387	0	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	1	0	0
T166	997	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133149421	164	0	0
T7	29041	0	0	0
T10	0	1	0	0
T24	7726	0	0	0
T25	41825	0	0	0
T28	409	0	0	0
T29	403	0	0	0
T33	410	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	631	0	0	0
T61	0	1	0	0
T89	674	0	0	0
T90	1387	0	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	1	0	0
T166	997	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T6
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	133149421	164	0	0
CgEnOn_A	133149421	164	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133149421	164	0	0
T7	29041	0	0	0
T10	0	1	0	0
T24	7726	0	0	0
T25	41825	0	0	0
T28	409	0	0	0
T29	403	0	0	0
T33	410	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	631	0	0	0
T61	0	1	0	0
T89	674	0	0	0
T90	1387	0	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	1	0	0
T166	997	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133149421	164	0	0
T7	29041	0	0	0
T10	0	1	0	0
T24	7726	0	0	0
T25	41825	0	0	0
T28	409	0	0	0
T29	403	0	0	0
T33	410	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	631	0	0	0
T61	0	1	0	0
T89	674	0	0	0
T90	1387	0	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	1	0	0
T166	997	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T6
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	534026253	164	0	0
CgEnOn_A	534026253	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534026253	164	0	0
T7	116271	0	0	0
T10	0	1	0	0
T24	54484	0	0	0
T25	166927	0	0	0
T28	1744	0	0	0
T29	1636	0	0	0
T33	1677	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	2630	0	0	0
T61	0	1	0	0
T89	2632	0	0	0
T90	5153	0	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	1	0	0
T166	4121	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534026253	156	0	0
T7	116271	0	0	0
T24	54484	0	0	0
T25	166927	0	0	0
T28	1744	0	0	0
T29	1636	0	0	0
T33	1677	1	0	0
T34	0	1	0	0
T35	0	3	0	0
T37	2630	0	0	0
T89	2632	0	0	0
T90	5153	0	0	0
T159	0	3	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	2	0	0
T163	0	1	0	0
T164	0	3	0	0
T165	0	4	0	0
T166	4121	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T6
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	568506940	153	0	0
CgEnOn_A	568506940	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	153	0	0
T7	121119	0	0	0
T24	56756	0	0	0
T25	179888	0	0	0
T28	1818	0	0	0
T29	1704	0	0	0
T33	1770	1	0	0
T34	0	3	0	0
T35	0	5	0	0
T37	2740	0	0	0
T89	2742	0	0	0
T90	5367	0	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	6	0	0
T166	4293	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	153	0	0
T7	121119	0	0	0
T24	56756	0	0	0
T25	179888	0	0	0
T28	1818	0	0	0
T29	1704	0	0	0
T33	1770	1	0	0
T34	0	3	0	0
T35	0	5	0	0
T37	2740	0	0	0
T89	2742	0	0	0
T90	5367	0	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	6	0	0
T166	4293	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T6
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	568506940	153	0	0
CgEnOn_A	568506940	153	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	153	0	0
T7	121119	0	0	0
T24	56756	0	0	0
T25	179888	0	0	0
T28	1818	0	0	0
T29	1704	0	0	0
T33	1770	1	0	0
T34	0	3	0	0
T35	0	5	0	0
T37	2740	0	0	0
T89	2742	0	0	0
T90	5367	0	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	6	0	0
T166	4293	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	153	0	0
T7	121119	0	0	0
T24	56756	0	0	0
T25	179888	0	0	0
T28	1818	0	0	0
T29	1704	0	0	0
T33	1770	1	0	0
T34	0	3	0	0
T35	0	5	0	0
T37	2740	0	0	0
T89	2742	0	0	0
T90	5367	0	0	0
T159	0	4	0	0
T160	0	5	0	0
T161	0	4	0	0
T162	0	4	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	6	0	0
T166	4293	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T6
1	0	Unreachable
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	272754415	153	0	0
CgEnOn_A	272754415	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272754415	153	0	0
T7	58138	0	0	0
T24	27243	0	0	0
T25	80587	0	0	0
T28	873	0	0	0
T29	817	0	0	0
T33	853	1	0	0
T34	0	3	0	0
T35	0	5	0	0
T37	1316	0	0	0
T89	1316	0	0	0
T90	2576	0	0	0
T159	0	2	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	6	0	0
T166	2061	0	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272754415	152	0	0
T7	58138	0	0	0
T24	27243	0	0	0
T25	80587	0	0	0
T28	873	0	0	0
T29	817	0	0	0
T33	853	1	0	0
T34	0	3	0	0
T35	0	5	0	0
T37	1316	0	0	0
T89	1316	0	0	0
T90	2576	0	0	0
T159	0	2	0	0
T160	0	5	0	0
T161	0	5	0	0
T162	0	3	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	0	6	0	0
T166	2061	0	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	133149421	7589	0	0
CgEnOn_A	133149421	5241	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133149421	7589	0	0
T1	59869	1	0	0
T2	59989	12	0	0
T4	1285	1	0	0
T5	311	1	0	0
T13	985	1	0	0
T14	914	2	0	0
T15	869	1	0	0
T16	729	1	0	0
T17	332	1	0	0
T18	1120	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	133149421	5241	0	0
T2	59989	9	0	0
T3	16282	0	0	0
T6	0	20	0	0
T14	914	1	0	0
T15	869	0	0	0
T16	729	0	0	0
T17	332	0	0	0
T18	1120	0	0	0
T19	22102	0	0	0
T22	20562	0	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T70	843	3	0	0
T166	0	10	0	0
T167	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	266300058	7612	0	0
CgEnOn_A	266300058	5264	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266300058	7612	0	0
T1	119739	1	0	0
T2	119981	10	0	0
T4	2570	1	0	0
T5	621	1	0	0
T13	1969	1	0	0
T14	1827	2	0	0
T15	1738	1	0	0
T16	1458	1	0	0
T17	664	1	0	0
T18	2246	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	266300058	5264	0	0
T2	119981	7	0	0
T3	32564	0	0	0
T6	0	20	0	0
T14	1827	1	0	0
T15	1738	0	0	0
T16	1458	0	0	0
T17	664	0	0	0
T18	2246	0	0	0
T19	44205	0	0	0
T22	41117	0	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T70	1685	2	0	0
T166	0	9	0	0
T167	0	17	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	534026253	7669	0	0
CgEnOn_A	534026253	5313	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534026253	7669	0	0
T1	239530	1	0	0
T2	236707	12	0	0
T4	4780	1	0	0
T5	1268	1	0	0
T13	3991	1	0	0
T14	3706	2	0	0
T15	3527	1	0	0
T16	2940	1	0	0
T17	1401	1	0	0
T18	2865	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	534026253	5313	0	0
T2	236707	9	0	0
T3	65153	0	0	0
T6	0	22	0	0
T14	3706	1	0	0
T15	3527	0	0	0
T16	2940	0	0	0
T17	1401	0	0	0
T18	2865	0	0	0
T19	88503	0	0	0
T22	145233	0	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	1	0	0
T70	3422	3	0	0
T166	0	10	0	0
T167	0	15	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T35
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	272754415	7643	0	0
CgEnOn_A	272754415	5287	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272754415	7643	0	0
T1	119770	1	0	0
T2	118359	13	0	0
T4	2390	1	0	0
T5	633	1	0	0
T13	1995	1	0	0
T14	1853	2	0	0
T15	1763	1	0	0
T16	1470	1	0	0
T17	701	1	0	0
T18	1432	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	272754415	5287	0	0
T2	118359	10	0	0
T3	32578	0	0	0
T6	0	19	0	0
T14	1853	1	0	0
T15	1763	0	0	0
T16	1470	0	0	0
T17	701	0	0	0
T18	1432	0	0	0
T19	44253	0	0	0
T22	72620	0	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	3	0	0
T37	0	1	0	0
T70	1711	2	0	0
T166	0	9	0	0
T167	0	13	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T6
1	0	Covered	T14,T15,T16
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	568506940	3953	0	0
CgEnOn_A	568506940	3953	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	3953	0	0
T2	246579	6	0	0
T3	67869	0	0	0
T6	0	23	0	0
T14	3861	1	0	0
T15	3674	11	0	0
T16	3063	10	0	0
T17	1459	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	3	0	0
T37	0	1	0	0
T70	3565	0	0	0
T71	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	3953	0	0
T2	246579	6	0	0
T3	67869	0	0	0
T6	0	23	0	0
T14	3861	1	0	0
T15	3674	11	0	0
T16	3063	10	0	0
T17	1459	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	3	0	0
T37	0	1	0	0
T70	3565	0	0	0
T71	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T6
1	0	Covered	T14,T15,T16
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	568506940	3944	0	0
CgEnOn_A	568506940	3944	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	3944	0	0
T2	246579	4	0	0
T3	67869	0	0	0
T6	0	22	0	0
T14	3861	1	0	0
T15	3674	9	0	0
T16	3063	10	0	0
T17	1459	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	3	0	0
T37	0	1	0	0
T70	3565	0	0	0
T71	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	3944	0	0
T2	246579	4	0	0
T3	67869	0	0	0
T6	0	22	0	0
T14	3861	1	0	0
T15	3674	9	0	0
T16	3063	10	0	0
T17	1459	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	3	0	0
T37	0	1	0	0
T70	3565	0	0	0
T71	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T6
1	0	Covered	T14,T15,T16
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	568506940	3975	0	0
CgEnOn_A	568506940	3975	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	3975	0	0
T2	246579	10	0	0
T3	67869	0	0	0
T6	0	33	0	0
T14	3861	1	0	0
T15	3674	8	0	0
T16	3063	11	0	0
T17	1459	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	3	0	0
T37	0	1	0	0
T70	3565	0	0	0
T71	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	3975	0	0
T2	246579	10	0	0
T3	67869	0	0	0
T6	0	33	0	0
T14	3861	1	0	0
T15	3674	8	0	0
T16	3063	11	0	0
T17	1459	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	3	0	0
T37	0	1	0	0
T70	3565	0	0	0
T71	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T22,T6
1	0	Covered	T14,T15,T16
1	1	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	568506940	4007	0	0
CgEnOn_A	568506940	4007	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	4007	0	0
T2	246579	6	0	0
T3	67869	0	0	0
T6	0	28	0	0
T14	3861	1	0	0
T15	3674	14	0	0
T16	3063	10	0	0
T17	1459	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	3	0	0
T37	0	1	0	0
T70	3565	0	0	0
T71	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	568506940	4007	0	0
T2	246579	6	0	0
T3	67869	0	0	0
T6	0	28	0	0
T14	3861	1	0	0
T15	3674	14	0	0
T16	3063	10	0	0
T17	1459	0	0	0
T18	2984	0	0	0
T19	92193	0	0	0
T22	151289	0	0	0
T25	0	1	0	0
T33	0	1	0	0
T34	0	3	0	0
T37	0	1	0	0
T70	3565	0	0	0
T71	0	6	0	0