Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	620001	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3535746

1

T4

139

T7

3

T25

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1020368	1			T4	144		T5	15		T26	3
values[0x0]	1440423	1			T4	75		T7	11		T25	14
values[0x1]	1694956	1			T4	63		T7	10		T25	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	342816	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3812931

1

T4

165

T7

4

T25

12

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16051	1			T4	1		T27	1		T2	190
valid_sources[0x01]	18467	1			T18	1		T2	214		T11	1
valid_sources[0x02]	15002	1			T18	1		T19	15		T2	215
valid_sources[0x03]	15862	1			T4	2		T2	200		T3	32
valid_sources[0x04]	16004	1			T4	2		T2	157		T20	3
valid_sources[0x05]	15913	1			T4	1		T2	199		T30	2
valid_sources[0x06]	17074	1			T2	181		T21	1		T30	1
valid_sources[0x07]	16151	1			T4	2		T2	192		T30	2
valid_sources[0x08]	15039	1			T4	1		T5	1		T1	5
valid_sources[0x09]	15172	1			T2	209		T30	3		T121	1
valid_sources[0x0a]	16376	1			T2	157		T20	1		T30	1
valid_sources[0x0b]	16972	1			T4	2		T5	7		T2	216
valid_sources[0x0c]	15681	1			T4	2		T27	1		T2	183
valid_sources[0x0d]	16247	1			T4	1		T5	2		T18	1
valid_sources[0x0e]	16067	1			T4	1		T18	1		T2	174
valid_sources[0x0f]	15872	1			T4	2		T2	148		T30	2
valid_sources[0x10]	15829	1			T4	3		T5	1		T2	157
valid_sources[0x11]	17402	1			T7	2		T27	1		T2	178
valid_sources[0x12]	16516	1			T25	35		T5	1		T18	1
valid_sources[0x13]	16565	1			T4	1		T7	1		T1	16
valid_sources[0x14]	15080	1			T4	1		T1	6		T2	207
valid_sources[0x15]	16652	1			T4	1		T28	81		T2	234
valid_sources[0x16]	16187	1			T4	1		T2	203		T30	2
valid_sources[0x17]	15028	1			T2	196		T21	2		T30	1
valid_sources[0x18]	16585	1			T4	2		T2	170		T30	3
valid_sources[0x19]	16836	1			T4	2		T5	1		T2	205
valid_sources[0x1a]	16361	1			T4	1		T5	1		T2	189
valid_sources[0x1b]	16944	1			T4	3		T27	1		T1	12
valid_sources[0x1c]	16531	1			T4	2		T2	213		T20	2
valid_sources[0x1d]	16107	1			T4	1		T5	5		T2	161
valid_sources[0x1e]	15731	1			T4	1		T2	206		T20	1
valid_sources[0x1f]	18283	1			T4	1		T1	3		T2	170
valid_sources[0x20]	16095	1			T4	2		T2	170		T20	1
valid_sources[0x21]	15040	1			T4	1		T2	220		T20	2
valid_sources[0x22]	15263	1			T4	1		T27	1		T2	205
valid_sources[0x23]	16198	1			T27	1		T2	191		T30	2
valid_sources[0x24]	16809	1			T18	1		T2	224		T20	1
valid_sources[0x25]	16572	1			T4	1		T2	175		T20	1
valid_sources[0x26]	15176	1			T4	1		T27	1		T2	207
valid_sources[0x27]	16574	1			T1	32		T2	178		T30	1
valid_sources[0x28]	15882	1			T4	1		T5	2		T2	187
valid_sources[0x29]	15953	1			T4	2		T5	5		T2	163
valid_sources[0x2a]	16086	1			T5	6		T2	180		T20	2
valid_sources[0x2b]	15047	1			T2	168		T20	1		T3	1
valid_sources[0x2c]	16054	1			T4	2		T2	191		T3	37
valid_sources[0x2d]	16541	1			T4	1		T7	1		T2	183
valid_sources[0x2e]	14998	1			T27	1		T2	170		T30	1
valid_sources[0x2f]	16356	1			T4	1		T5	1		T2	207
valid_sources[0x30]	16645	1			T5	2		T2	164		T20	3
valid_sources[0x31]	15766	1			T5	4		T2	149		T30	1
valid_sources[0x32]	15916	1			T27	1		T2	185		T30	2
valid_sources[0x33]	15901	1			T2	147		T30	2		T31	2
valid_sources[0x34]	16457	1			T4	1		T5	2		T2	204
valid_sources[0x35]	14916	1			T4	2		T7	1		T2	173
valid_sources[0x36]	16192	1			T4	1		T5	1		T2	171
valid_sources[0x37]	16907	1			T4	1		T2	197		T3	19
valid_sources[0x38]	15801	1			T4	1		T5	2		T27	1
valid_sources[0x39]	15787	1			T4	1		T5	7		T26	1
valid_sources[0x3a]	15736	1			T5	1		T2	205		T21	1
valid_sources[0x3b]	15183	1			T4	1		T27	2		T2	151
valid_sources[0x3c]	15300	1			T4	1		T18	1		T2	177
valid_sources[0x3d]	15901	1			T4	1		T1	6		T18	1
valid_sources[0x3e]	15651	1			T5	3		T27	2		T2	184
valid_sources[0x3f]	15412	1			T4	1		T18	1		T2	179
valid_sources[0x40]	16123	1			T2	202		T20	1		T22	1
valid_sources[0x41]	16232	1			T4	1		T5	3		T27	2
valid_sources[0x42]	16331	1			T2	218		T20	1		T30	2
valid_sources[0x43]	16689	1			T4	2		T5	3		T18	3
valid_sources[0x44]	16688	1			T2	208		T20	1		T30	2
valid_sources[0x45]	16607	1			T4	1		T18	3		T2	225
valid_sources[0x46]	16638	1			T4	1		T1	5		T2	169
valid_sources[0x47]	17459	1			T4	1		T26	2		T27	1
valid_sources[0x48]	15543	1			T4	1		T2	167		T30	2
valid_sources[0x49]	15931	1			T18	1		T2	181		T20	6
valid_sources[0x4a]	15435	1			T4	1		T2	179		T20	1
valid_sources[0x4b]	15638	1			T4	2		T27	1		T19	11
valid_sources[0x4c]	15560	1			T27	3		T2	190		T20	3
valid_sources[0x4d]	17154	1			T2	181		T20	3		T30	2
valid_sources[0x4e]	15713	1			T4	2		T5	2		T1	2
valid_sources[0x4f]	15401	1			T4	3		T2	213		T20	2
valid_sources[0x50]	15396	1			T5	2		T27	1		T18	3
valid_sources[0x51]	16095	1			T4	1		T2	170		T20	1
valid_sources[0x52]	16595	1			T4	2		T1	2		T2	166
valid_sources[0x53]	17777	1			T4	1		T5	1		T1	2
valid_sources[0x54]	15784	1			T5	1		T18	2		T2	177
valid_sources[0x55]	17202	1			T4	2		T18	2		T2	172
valid_sources[0x56]	16380	1			T27	1		T2	189		T20	3
valid_sources[0x57]	16789	1			T27	1		T2	182		T30	2
valid_sources[0x58]	16407	1			T5	12		T27	1		T2	225
valid_sources[0x59]	15370	1			T4	1		T5	10		T27	1
valid_sources[0x5a]	16561	1			T4	2		T2	215		T20	1
valid_sources[0x5b]	16594	1			T4	1		T5	1		T2	172
valid_sources[0x5c]	16502	1			T5	1		T27	1		T2	175
valid_sources[0x5d]	15959	1			T4	1		T2	157		T30	1
valid_sources[0x5e]	15682	1			T4	1		T5	2		T1	7
valid_sources[0x5f]	15944	1			T4	3		T5	4		T2	161
valid_sources[0x60]	15719	1			T5	9		T2	240		T20	1
valid_sources[0x61]	15777	1			T27	1		T2	192		T30	1
valid_sources[0x62]	15580	1			T5	3		T2	173		T21	1
valid_sources[0x63]	15355	1			T4	2		T2	207		T3	22
valid_sources[0x64]	17649	1			T4	3		T27	2		T18	1
valid_sources[0x65]	19884	1			T4	1		T1	1		T2	213
valid_sources[0x66]	16275	1			T7	1		T5	3		T2	176
valid_sources[0x67]	20242	1			T4	1		T1	14		T2	211
valid_sources[0x68]	16942	1			T5	2		T27	1		T2	173
valid_sources[0x69]	16247	1			T5	1		T2	168		T11	1
valid_sources[0x6a]	16915	1			T4	1		T5	2		T2	218
valid_sources[0x6b]	16211	1			T5	2		T2	169		T22	1
valid_sources[0x6c]	16174	1			T4	1		T2	164		T30	1
valid_sources[0x6d]	16151	1			T2	186		T20	1		T21	1
valid_sources[0x6e]	15488	1			T27	2		T2	192		T20	1
valid_sources[0x6f]	15872	1			T4	1		T5	1		T1	29
valid_sources[0x70]	16302	1			T2	181		T20	1		T30	4
valid_sources[0x71]	15907	1			T2	240		T20	2		T30	1
valid_sources[0x72]	15110	1			T4	2		T1	1		T2	172
valid_sources[0x73]	15391	1			T4	2		T5	2		T2	202
valid_sources[0x74]	15324	1			T4	1		T2	162		T20	4
valid_sources[0x75]	16533	1			T4	1		T27	1		T2	160
valid_sources[0x76]	15661	1			T4	1		T2	196		T20	4
valid_sources[0x77]	16006	1			T2	206		T30	5		T11	1
valid_sources[0x78]	17715	1			T1	3		T2	185		T20	3
valid_sources[0x79]	16130	1			T4	1		T5	5		T2	225
valid_sources[0x7a]	16484	1			T1	5		T2	186		T21	1
valid_sources[0x7b]	16951	1			T4	1		T27	1		T2	197
valid_sources[0x7c]	17737	1			T19	2		T2	179		T20	6
valid_sources[0x7d]	16063	1			T4	1		T5	2		T2	181
valid_sources[0x7e]	15619	1			T4	1		T27	1		T18	1
valid_sources[0x7f]	16164	1			T4	3		T27	1		T2	204
valid_sources[0x80]	15809	1			T4	2		T27	2		T2	178

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

891055

1

T4

75

T5

7

T26

2

values[0x0]

all_enables

biggest_size

1344980

1

T4

47

T7

3

T25

3

values[0x1]

all_enables

biggest_size

1299711

1

T4

17

T25

3

T5

41