Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
329871 |
1 |
|
|
T6 |
2 |
|
T4 |
14 |
|
T7 |
52 |
auto[1] |
223646166 |
1 |
|
|
T6 |
1073 |
|
T4 |
2093 |
|
T7 |
675 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8706 |
1 |
|
|
T6 |
13 |
|
T4 |
14 |
|
T7 |
2 |
auto[1] |
223967331 |
1 |
|
|
T6 |
1062 |
|
T4 |
2093 |
|
T7 |
725 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
122211605 |
1 |
|
|
T6 |
1075 |
|
T4 |
2101 |
|
T7 |
24 |
auto[1] |
101764432 |
1 |
|
|
T4 |
6 |
|
T7 |
703 |
|
T25 |
74 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5340 |
1 |
|
|
T6 |
2 |
|
T4 |
12 |
|
T25 |
2 |
auto[0] |
auto[0] |
auto[1] |
1664 |
1 |
|
|
T4 |
2 |
|
T7 |
2 |
|
T5 |
2 |
auto[0] |
auto[1] |
auto[0] |
253253 |
1 |
|
|
T7 |
7 |
|
T25 |
104 |
|
T27 |
6 |
auto[0] |
auto[1] |
auto[1] |
69614 |
1 |
|
|
T7 |
43 |
|
T25 |
51 |
|
T2 |
355 |
auto[1] |
auto[1] |
auto[0] |
121951310 |
1 |
|
|
T6 |
1062 |
|
T4 |
2089 |
|
T7 |
17 |
auto[1] |
auto[1] |
auto[1] |
101693154 |
1 |
|
|
T4 |
4 |
|
T7 |
658 |
|
T25 |
23 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
163770 |
1 |
|
|
T6 |
2 |
|
T4 |
14 |
|
T7 |
27 |
auto[1] |
111822327 |
1 |
|
|
T6 |
535 |
|
T4 |
1040 |
|
T7 |
336 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7869 |
1 |
|
|
T6 |
7 |
|
T4 |
14 |
|
T7 |
2 |
auto[1] |
111978228 |
1 |
|
|
T6 |
530 |
|
T4 |
1040 |
|
T7 |
361 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
61103910 |
1 |
|
|
T6 |
537 |
|
T4 |
1051 |
|
T7 |
12 |
auto[1] |
50882187 |
1 |
|
|
T4 |
3 |
|
T7 |
351 |
|
T25 |
36 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5340 |
1 |
|
|
T6 |
2 |
|
T4 |
12 |
|
T25 |
2 |
auto[0] |
auto[0] |
auto[1] |
1664 |
1 |
|
|
T4 |
2 |
|
T7 |
2 |
|
T5 |
2 |
auto[0] |
auto[1] |
auto[0] |
123029 |
1 |
|
|
T7 |
7 |
|
T25 |
59 |
|
T27 |
3 |
auto[0] |
auto[1] |
auto[1] |
33737 |
1 |
|
|
T7 |
18 |
|
T25 |
18 |
|
T2 |
323 |
auto[1] |
auto[1] |
auto[0] |
60974676 |
1 |
|
|
T6 |
530 |
|
T4 |
1039 |
|
T7 |
5 |
auto[1] |
auto[1] |
auto[1] |
50846786 |
1 |
|
|
T4 |
1 |
|
T7 |
331 |
|
T25 |
18 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
643440 |
1 |
|
|
T6 |
2 |
|
T4 |
14 |
|
T7 |
102 |
auto[1] |
446760557 |
1 |
|
|
T6 |
2148 |
|
T4 |
4196 |
|
T7 |
1351 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10420 |
1 |
|
|
T6 |
24 |
|
T4 |
14 |
|
T7 |
2 |
auto[1] |
447393577 |
1 |
|
|
T6 |
2126 |
|
T4 |
4196 |
|
T7 |
1451 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
243875263 |
1 |
|
|
T6 |
2150 |
|
T4 |
4199 |
|
T7 |
49 |
auto[1] |
203528734 |
1 |
|
|
T4 |
11 |
|
T7 |
1404 |
|
T25 |
147 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5340 |
1 |
|
|
T6 |
2 |
|
T4 |
12 |
|
T25 |
2 |
auto[0] |
auto[0] |
auto[1] |
1664 |
1 |
|
|
T4 |
2 |
|
T7 |
2 |
|
T5 |
2 |
auto[0] |
auto[1] |
auto[0] |
502697 |
1 |
|
|
T7 |
23 |
|
T25 |
240 |
|
T27 |
12 |
auto[0] |
auto[1] |
auto[1] |
133739 |
1 |
|
|
T7 |
77 |
|
T25 |
74 |
|
T2 |
756 |
auto[1] |
auto[1] |
auto[0] |
243363810 |
1 |
|
|
T6 |
2126 |
|
T4 |
4187 |
|
T7 |
26 |
auto[1] |
auto[1] |
auto[1] |
203393331 |
1 |
|
|
T4 |
9 |
|
T7 |
1325 |
|
T25 |
73 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |
Summary for Variable csr_enable_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for csr_enable_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
318080 |
1 |
|
|
T6 |
2 |
|
T4 |
14 |
|
T7 |
52 |
auto[1] |
228814696 |
1 |
|
|
T6 |
1050 |
|
T4 |
2092 |
|
T7 |
675 |
Summary for Variable ip_clk_en_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for ip_clk_en_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8242 |
1 |
|
|
T6 |
11 |
|
T4 |
14 |
|
T7 |
2 |
auto[1] |
229124534 |
1 |
|
|
T6 |
1041 |
|
T4 |
2092 |
|
T7 |
725 |
Summary for Variable scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for scanmode_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
125149005 |
1 |
|
|
T6 |
1052 |
|
T4 |
2101 |
|
T7 |
24 |
auto[1] |
103983771 |
1 |
|
|
T4 |
5 |
|
T7 |
703 |
|
T25 |
73 |
Summary for Cross peri_cross
Samples crossed: csr_enable_cp ip_clk_en_cp scanmode_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
6 |
0 |
6 |
100.00 |
|
Automatically Generated Cross Bins |
6 |
0 |
6 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for peri_cross
Bins
csr_enable_cp | ip_clk_en_cp | scanmode_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
auto[0] |
5324 |
1 |
|
|
T6 |
2 |
|
T4 |
12 |
|
T25 |
2 |
auto[0] |
auto[0] |
auto[1] |
1680 |
1 |
|
|
T4 |
2 |
|
T7 |
2 |
|
T5 |
2 |
auto[0] |
auto[1] |
auto[0] |
243721 |
1 |
|
|
T7 |
13 |
|
T25 |
129 |
|
T27 |
6 |
auto[0] |
auto[1] |
auto[1] |
67355 |
1 |
|
|
T7 |
37 |
|
T25 |
27 |
|
T2 |
479 |
auto[1] |
auto[1] |
auto[0] |
124898722 |
1 |
|
|
T6 |
1041 |
|
T4 |
2089 |
|
T7 |
11 |
auto[1] |
auto[1] |
auto[1] |
103914736 |
1 |
|
|
T4 |
3 |
|
T7 |
664 |
|
T25 |
46 |
User Defined Cross Bins for peri_cross
Excluded/Illegal bins
NAME | COUNT | STATUS |
ignore_enable_off |
0 |
Excluded |