Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T7,T25,T2
1	0	Covered	T6,T4,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T25
1	0	Covered	T6,T23,T37
1	1	Covered	T6,T4,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1015857684	14148	0	0
GateOpen_A	1015857684	20524	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1015857684	14148	0	0
T1	431480	0	0	0
T2	0	124	0	0
T3	0	36	0	0
T4	89416	0	0	0
T5	230547	0	0	0
T6	5142	4	0	0
T7	3586	8	0	0
T18	9006	0	0	0
T23	0	14	0	0
T25	8596	52	0	0
T26	3091	0	0	0
T27	10700	4	0	0
T28	9185	4	0	0
T31	0	36	0	0
T37	0	19	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1015857684	20524	0	0
T1	431480	0	0	0
T2	0	124	0	0
T4	89416	24	0	0
T5	230547	0	0	0
T6	5142	8	0	0
T7	3586	8	0	0
T18	9006	0	0	0
T20	0	4	0	0
T22	0	4	0	0
T25	8596	56	0	0
T26	3091	4	0	0
T27	10700	8	0	0
T28	9185	8	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T7,T25,T2
1	0	Covered	T6,T4,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T25
1	0	Covered	T6,T23,T37
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	112000841	3353	0	0
GateOpen_A	112000841	4946	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112000841	3353	0	0
T1	47936	0	0	0
T2	0	28	0	0
T3	0	7	0	0
T4	6486	0	0	0
T5	25601	0	0	0
T6	566	1	0	0
T7	388	2	0	0
T18	997	0	0	0
T23	0	3	0	0
T25	951	13	0	0
T26	346	0	0	0
T27	1167	1	0	0
T28	1003	1	0	0
T31	0	10	0	0
T37	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112000841	4946	0	0
T1	47936	0	0	0
T2	0	28	0	0
T4	6486	6	0	0
T5	25601	0	0	0
T6	566	2	0	0
T7	388	2	0	0
T18	997	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T25	951	14	0	0
T26	346	1	0	0
T27	1167	2	0	0
T28	1003	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T7,T25,T2
1	0	Covered	T6,T4,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T25
1	0	Covered	T6,T23,T37
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	224002575	3583	0	0
GateOpen_A	224002575	5176	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224002575	3583	0	0
T1	95871	0	0	0
T2	0	33	0	0
T3	0	9	0	0
T4	12969	0	0	0
T5	51201	0	0	0
T6	1131	1	0	0
T7	775	2	0	0
T18	1993	0	0	0
T23	0	3	0	0
T25	1902	12	0	0
T26	693	0	0	0
T27	2333	1	0	0
T28	2006	1	0	0
T31	0	9	0	0
T37	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224002575	5176	0	0
T1	95871	0	0	0
T2	0	33	0	0
T4	12969	6	0	0
T5	51201	0	0	0
T6	1131	2	0	0
T7	775	2	0	0
T18	1993	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T25	1902	13	0	0
T26	693	1	0	0
T27	2333	2	0	0
T28	2006	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T7,T25,T2
1	0	Covered	T6,T4,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T25
1	0	Covered	T6,T23,T37
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	449598295	3629	0	0
GateOpen_A	449598295	5224	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449598295	3629	0	0
T1	191779	0	0	0
T2	0	32	0	0
T3	0	12	0	0
T4	46640	0	0	0
T5	102495	0	0	0
T6	2312	1	0	0
T7	1615	2	0	0
T18	4010	0	0	0
T23	0	3	0	0
T25	3829	13	0	0
T26	1368	0	0	0
T27	4800	1	0	0
T28	4117	1	0	0
T31	0	9	0	0
T37	0	5	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449598295	5224	0	0
T1	191779	0	0	0
T2	0	32	0	0
T4	46640	6	0	0
T5	102495	0	0	0
T6	2312	2	0	0
T7	1615	2	0	0
T18	4010	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T25	3829	14	0	0
T26	1368	1	0	0
T27	4800	2	0	0
T28	4117	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Covered	T7,T25,T2
1	0	Covered	T6,T4,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T25
1	0	Covered	T6,T23,T37
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	230255973	3583	0	0
GateOpen_A	230255973	5178	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230255973	3583	0	0
T1	95894	0	0	0
T2	0	31	0	0
T3	0	8	0	0
T4	23321	0	0	0
T5	51250	0	0	0
T6	1133	1	0	0
T7	808	2	0	0
T18	2006	0	0	0
T23	0	5	0	0
T25	1914	14	0	0
T26	684	0	0	0
T27	2400	1	0	0
T28	2059	1	0	0
T31	0	8	0	0
T37	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230255973	5178	0	0
T1	95894	0	0	0
T2	0	31	0	0
T4	23321	6	0	0
T5	51250	0	0	0
T6	1133	2	0	0
T7	808	2	0	0
T18	2006	0	0	0
T20	0	1	0	0
T22	0	1	0	0
T25	1914	15	0	0
T26	684	1	0	0
T27	2400	2	0	0
T28	2059	2	0	0