Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	839995625	77979	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	839995625	77979	0	0
T1	948965	290	0	0
T2	933625	480	0	0
T3	2776810	396	0	0
T11	0	106	0	0
T12	0	746	0	0
T13	0	281	0	0
T14	0	70	0	0
T15	0	199	0	0
T16	0	167	0	0
T17	0	1404	0	0
T18	10235	0	0	0
T19	13430	0	0	0
T20	635020	0	0	0
T21	7050	0	0	0
T22	4655	0	0	0
T23	8345	0	0	0
T24	7865	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167999125	11449	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	11449	0	0
T1	189793	39	0	0
T2	186725	81	0	0
T3	555362	50	0	0
T11	0	17	0	0
T12	0	110	0	0
T13	0	41	0	0
T14	0	10	0	0
T15	0	25	0	0
T16	0	27	0	0
T17	0	187	0	0
T18	2047	0	0	0
T19	2686	0	0	0
T20	127004	0	0	0
T21	1410	0	0	0
T22	931	0	0	0
T23	1669	0	0	0
T24	1573	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167999125	11340	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	11340	0	0
T1	189793	38	0	0
T2	186725	75	0	0
T3	555362	57	0	0
T11	0	17	0	0
T12	0	109	0	0
T13	0	41	0	0
T14	0	10	0	0
T15	0	29	0	0
T16	0	27	0	0
T17	0	180	0	0
T18	2047	0	0	0
T19	2686	0	0	0
T20	127004	0	0	0
T21	1410	0	0	0
T22	931	0	0	0
T23	1669	0	0	0
T24	1573	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167999125	15690	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	15690	0	0
T1	189793	59	0	0
T2	186725	97	0	0
T3	555362	77	0	0
T11	0	21	0	0
T12	0	150	0	0
T13	0	56	0	0
T14	0	15	0	0
T15	0	39	0	0
T16	0	34	0	0
T17	0	285	0	0
T18	2047	0	0	0
T19	2686	0	0	0
T20	127004	0	0	0
T21	1410	0	0	0
T22	931	0	0	0
T23	1669	0	0	0
T24	1573	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167999125	15684	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	15684	0	0
T1	189793	58	0	0
T2	186725	95	0	0
T3	555362	79	0	0
T11	0	22	0	0
T12	0	148	0	0
T13	0	56	0	0
T14	0	14	0	0
T15	0	41	0	0
T16	0	34	0	0
T17	0	288	0	0
T18	2047	0	0	0
T19	2686	0	0	0
T20	127004	0	0	0
T21	1410	0	0	0
T22	931	0	0	0
T23	1669	0	0	0
T24	1573	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	167999125	23816	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	23816	0	0
T1	189793	96	0	0
T2	186725	132	0	0
T3	555362	133	0	0
T11	0	29	0	0
T12	0	229	0	0
T13	0	87	0	0
T14	0	21	0	0
T15	0	65	0	0
T16	0	45	0	0
T17	0	464	0	0
T18	2047	0	0	0
T19	2686	0	0	0
T20	127004	0	0	0
T21	1410	0	0	0
T22	931	0	0	0
T23	1669	0	0	0
T24	1573	0	0	0