Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Line Coverage for Module :
prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Module :
prim_mubi4_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
Branch Coverage for Module :
prim_mubi4_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
Assert Coverage for Module :
prim_mubi4_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22540 |
22540 |
0 |
0 |
T1 |
28 |
28 |
0 |
0 |
T4 |
28 |
28 |
0 |
0 |
T5 |
28 |
28 |
0 |
0 |
T6 |
28 |
28 |
0 |
0 |
T7 |
28 |
28 |
0 |
0 |
T18 |
28 |
28 |
0 |
0 |
T25 |
28 |
28 |
0 |
0 |
T26 |
28 |
28 |
0 |
0 |
T27 |
28 |
28 |
0 |
0 |
T28 |
28 |
28 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
5078344 |
5076090 |
0 |
0 |
T4 |
1219507 |
183043 |
0 |
0 |
T5 |
1652672 |
1649837 |
0 |
0 |
T6 |
45065 |
42285 |
0 |
0 |
T7 |
43208 |
39231 |
0 |
0 |
T18 |
79274 |
77450 |
0 |
0 |
T25 |
60038 |
58636 |
0 |
0 |
T26 |
37037 |
33660 |
0 |
0 |
T27 |
77985 |
74834 |
0 |
0 |
T28 |
80719 |
77798 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1007994750 |
993077886 |
0 |
14490 |
T1 |
1138758 |
1138188 |
0 |
18 |
T4 |
276942 |
24888 |
0 |
18 |
T5 |
153738 |
153420 |
0 |
18 |
T6 |
6990 |
6486 |
0 |
18 |
T7 |
9798 |
8796 |
0 |
18 |
T18 |
12282 |
11940 |
0 |
18 |
T25 |
5028 |
4866 |
0 |
18 |
T26 |
8466 |
7614 |
0 |
18 |
T27 |
7494 |
7140 |
0 |
18 |
T28 |
12354 |
11850 |
0 |
18 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
16905 |
T1 |
1370469 |
1369783 |
0 |
21 |
T4 |
333289 |
29949 |
0 |
21 |
T5 |
580812 |
579640 |
0 |
21 |
T6 |
14110 |
13089 |
0 |
21 |
T7 |
11613 |
10426 |
0 |
21 |
T18 |
24816 |
24132 |
0 |
21 |
T25 |
21452 |
20828 |
0 |
21 |
T26 |
9890 |
8892 |
0 |
21 |
T27 |
27298 |
26044 |
0 |
21 |
T28 |
25387 |
24366 |
0 |
21 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
201102 |
0 |
0 |
T1 |
1370469 |
4 |
0 |
0 |
T2 |
1082387 |
242 |
0 |
0 |
T3 |
0 |
236 |
0 |
0 |
T4 |
194336 |
28 |
0 |
0 |
T5 |
427072 |
4 |
0 |
0 |
T6 |
9468 |
20 |
0 |
0 |
T7 |
6732 |
42 |
0 |
0 |
T12 |
0 |
464 |
0 |
0 |
T13 |
0 |
69 |
0 |
0 |
T18 |
24816 |
105 |
0 |
0 |
T19 |
8002 |
126 |
0 |
0 |
T20 |
347782 |
0 |
0 |
0 |
T21 |
4174 |
0 |
0 |
0 |
T22 |
6334 |
0 |
0 |
0 |
T25 |
15948 |
61 |
0 |
0 |
T26 |
9890 |
39 |
0 |
0 |
T27 |
27298 |
16 |
0 |
0 |
T28 |
25387 |
16 |
0 |
0 |
T31 |
0 |
140 |
0 |
0 |
T54 |
0 |
158 |
0 |
0 |
T56 |
0 |
13 |
0 |
0 |
T117 |
0 |
30 |
0 |
0 |
T118 |
0 |
45 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
2569117 |
2568080 |
0 |
0 |
T4 |
609276 |
127933 |
0 |
0 |
T5 |
918122 |
916738 |
0 |
0 |
T6 |
23965 |
22671 |
0 |
0 |
T7 |
21797 |
19970 |
0 |
0 |
T18 |
42176 |
41339 |
0 |
0 |
T25 |
33558 |
32903 |
0 |
0 |
T26 |
18681 |
17115 |
0 |
0 |
T27 |
43193 |
41611 |
0 |
0 |
T28 |
42978 |
41543 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T26,T19,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T26,T19,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T26,T19,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T26,T19,T2 |
Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T19,T2 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T19,T2 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T19,T2 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T19,T2 |
0 |
Covered |
T6,T4,T7 |
Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449597862 |
445265813 |
0 |
0 |
T1 |
191779 |
191686 |
0 |
0 |
T4 |
46639 |
4210 |
0 |
0 |
T5 |
102494 |
102291 |
0 |
0 |
T6 |
2312 |
2150 |
0 |
0 |
T7 |
1615 |
1453 |
0 |
0 |
T18 |
4010 |
3903 |
0 |
0 |
T25 |
3828 |
3721 |
0 |
0 |
T26 |
1368 |
1233 |
0 |
0 |
T27 |
4800 |
4583 |
0 |
0 |
T28 |
4117 |
3955 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449597862 |
445258874 |
0 |
2415 |
T1 |
191779 |
191683 |
0 |
3 |
T4 |
46639 |
4189 |
0 |
3 |
T5 |
102494 |
102288 |
0 |
3 |
T6 |
2312 |
2147 |
0 |
3 |
T7 |
1615 |
1450 |
0 |
3 |
T18 |
4010 |
3900 |
0 |
3 |
T25 |
3828 |
3718 |
0 |
3 |
T26 |
1368 |
1230 |
0 |
3 |
T27 |
4800 |
4580 |
0 |
3 |
T28 |
4117 |
3952 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449597862 |
28918 |
0 |
0 |
T1 |
191779 |
0 |
0 |
0 |
T2 |
708937 |
95 |
0 |
0 |
T3 |
0 |
105 |
0 |
0 |
T12 |
0 |
189 |
0 |
0 |
T18 |
4010 |
0 |
0 |
0 |
T19 |
2630 |
63 |
0 |
0 |
T20 |
93774 |
0 |
0 |
0 |
T21 |
1354 |
0 |
0 |
0 |
T22 |
4472 |
0 |
0 |
0 |
T26 |
1368 |
6 |
0 |
0 |
T27 |
4800 |
0 |
0 |
0 |
T28 |
4117 |
0 |
0 |
0 |
T31 |
0 |
56 |
0 |
0 |
T54 |
0 |
80 |
0 |
0 |
T56 |
0 |
7 |
0 |
0 |
T117 |
0 |
16 |
0 |
0 |
T118 |
0 |
17 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T26,T19,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T26,T19,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T26,T19,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T26,T19,T2 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T19,T2 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T19,T2 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T19,T2 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T19,T2 |
0 |
Covered |
T6,T4,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165512981 |
0 |
2415 |
T1 |
189793 |
189698 |
0 |
3 |
T4 |
46157 |
4148 |
0 |
3 |
T5 |
25623 |
25570 |
0 |
3 |
T6 |
1165 |
1081 |
0 |
3 |
T7 |
1633 |
1466 |
0 |
3 |
T18 |
2047 |
1990 |
0 |
3 |
T25 |
838 |
811 |
0 |
3 |
T26 |
1411 |
1269 |
0 |
3 |
T27 |
1249 |
1190 |
0 |
3 |
T28 |
2059 |
1975 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
18258 |
0 |
0 |
T1 |
189793 |
0 |
0 |
0 |
T2 |
186725 |
74 |
0 |
0 |
T3 |
0 |
63 |
0 |
0 |
T12 |
0 |
130 |
0 |
0 |
T13 |
0 |
69 |
0 |
0 |
T18 |
2047 |
0 |
0 |
0 |
T19 |
2686 |
33 |
0 |
0 |
T20 |
127004 |
0 |
0 |
0 |
T21 |
1410 |
0 |
0 |
0 |
T22 |
931 |
0 |
0 |
0 |
T26 |
1411 |
11 |
0 |
0 |
T27 |
1249 |
0 |
0 |
0 |
T28 |
2059 |
0 |
0 |
0 |
T31 |
0 |
31 |
0 |
0 |
T54 |
0 |
37 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
T118 |
0 |
9 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T26,T19,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T26,T19,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T26,T19,T2 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T26,T19,T2 |
Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T19,T2 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T19,T2 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T19,T2 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T26,T19,T2 |
0 |
Covered |
T6,T4,T7 |
Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165512981 |
0 |
2415 |
T1 |
189793 |
189698 |
0 |
3 |
T4 |
46157 |
4148 |
0 |
3 |
T5 |
25623 |
25570 |
0 |
3 |
T6 |
1165 |
1081 |
0 |
3 |
T7 |
1633 |
1466 |
0 |
3 |
T18 |
2047 |
1990 |
0 |
3 |
T25 |
838 |
811 |
0 |
3 |
T26 |
1411 |
1269 |
0 |
3 |
T27 |
1249 |
1190 |
0 |
3 |
T28 |
2059 |
1975 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
20812 |
0 |
0 |
T1 |
189793 |
0 |
0 |
0 |
T2 |
186725 |
73 |
0 |
0 |
T3 |
0 |
68 |
0 |
0 |
T12 |
0 |
145 |
0 |
0 |
T18 |
2047 |
0 |
0 |
0 |
T19 |
2686 |
30 |
0 |
0 |
T20 |
127004 |
0 |
0 |
0 |
T21 |
1410 |
0 |
0 |
0 |
T22 |
931 |
0 |
0 |
0 |
T26 |
1411 |
8 |
0 |
0 |
T27 |
1249 |
0 |
0 |
0 |
T28 |
2059 |
0 |
0 |
0 |
T31 |
0 |
53 |
0 |
0 |
T54 |
0 |
41 |
0 |
0 |
T56 |
0 |
3 |
0 |
0 |
T117 |
0 |
14 |
0 |
0 |
T118 |
0 |
19 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
477257402 |
0 |
0 |
T1 |
199776 |
199736 |
0 |
0 |
T4 |
48584 |
27015 |
0 |
0 |
T5 |
106768 |
106671 |
0 |
0 |
T6 |
2367 |
2313 |
0 |
0 |
T7 |
1683 |
1614 |
0 |
0 |
T18 |
4178 |
4151 |
0 |
0 |
T25 |
3987 |
3961 |
0 |
0 |
T26 |
1425 |
1356 |
0 |
0 |
T27 |
5000 |
4860 |
0 |
0 |
T28 |
4288 |
4176 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
477257402 |
0 |
0 |
T1 |
199776 |
199736 |
0 |
0 |
T4 |
48584 |
27015 |
0 |
0 |
T5 |
106768 |
106671 |
0 |
0 |
T6 |
2367 |
2313 |
0 |
0 |
T7 |
1683 |
1614 |
0 |
0 |
T18 |
4178 |
4151 |
0 |
0 |
T25 |
3987 |
3961 |
0 |
0 |
T26 |
1425 |
1356 |
0 |
0 |
T27 |
5000 |
4860 |
0 |
0 |
T28 |
4288 |
4176 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449597862 |
447460781 |
0 |
0 |
T1 |
191779 |
191741 |
0 |
0 |
T4 |
46639 |
25934 |
0 |
0 |
T5 |
102494 |
102401 |
0 |
0 |
T6 |
2312 |
2260 |
0 |
0 |
T7 |
1615 |
1549 |
0 |
0 |
T18 |
4010 |
3985 |
0 |
0 |
T25 |
3828 |
3803 |
0 |
0 |
T26 |
1368 |
1302 |
0 |
0 |
T27 |
4800 |
4665 |
0 |
0 |
T28 |
4117 |
4010 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
449597862 |
447460781 |
0 |
0 |
T1 |
191779 |
191741 |
0 |
0 |
T4 |
46639 |
25934 |
0 |
0 |
T5 |
102494 |
102401 |
0 |
0 |
T6 |
2312 |
2260 |
0 |
0 |
T7 |
1615 |
1549 |
0 |
0 |
T18 |
4010 |
3985 |
0 |
0 |
T25 |
3828 |
3803 |
0 |
0 |
T26 |
1368 |
1302 |
0 |
0 |
T27 |
4800 |
4665 |
0 |
0 |
T28 |
4117 |
4010 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
224002167 |
224002167 |
0 |
0 |
T1 |
95871 |
95871 |
0 |
0 |
T4 |
12969 |
12969 |
0 |
0 |
T5 |
51201 |
51201 |
0 |
0 |
T6 |
1130 |
1130 |
0 |
0 |
T7 |
775 |
775 |
0 |
0 |
T18 |
1993 |
1993 |
0 |
0 |
T25 |
1902 |
1902 |
0 |
0 |
T26 |
692 |
692 |
0 |
0 |
T27 |
2333 |
2333 |
0 |
0 |
T28 |
2005 |
2005 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
224002167 |
224002167 |
0 |
0 |
T1 |
95871 |
95871 |
0 |
0 |
T4 |
12969 |
12969 |
0 |
0 |
T5 |
51201 |
51201 |
0 |
0 |
T6 |
1130 |
1130 |
0 |
0 |
T7 |
775 |
775 |
0 |
0 |
T18 |
1993 |
1993 |
0 |
0 |
T25 |
1902 |
1902 |
0 |
0 |
T26 |
692 |
692 |
0 |
0 |
T27 |
2333 |
2333 |
0 |
0 |
T28 |
2005 |
2005 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112000421 |
112000421 |
0 |
0 |
T1 |
47935 |
47935 |
0 |
0 |
T4 |
6485 |
6485 |
0 |
0 |
T5 |
25600 |
25600 |
0 |
0 |
T6 |
565 |
565 |
0 |
0 |
T7 |
387 |
387 |
0 |
0 |
T18 |
996 |
996 |
0 |
0 |
T25 |
951 |
951 |
0 |
0 |
T26 |
346 |
346 |
0 |
0 |
T27 |
1166 |
1166 |
0 |
0 |
T28 |
1003 |
1003 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
112000421 |
112000421 |
0 |
0 |
T1 |
47935 |
47935 |
0 |
0 |
T4 |
6485 |
6485 |
0 |
0 |
T5 |
25600 |
25600 |
0 |
0 |
T6 |
565 |
565 |
0 |
0 |
T7 |
387 |
387 |
0 |
0 |
T18 |
996 |
996 |
0 |
0 |
T25 |
951 |
951 |
0 |
0 |
T26 |
346 |
346 |
0 |
0 |
T27 |
1166 |
1166 |
0 |
0 |
T28 |
1003 |
1003 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
230255580 |
229176436 |
0 |
0 |
T1 |
95894 |
95875 |
0 |
0 |
T4 |
23321 |
12968 |
0 |
0 |
T5 |
51249 |
51203 |
0 |
0 |
T6 |
1133 |
1107 |
0 |
0 |
T7 |
807 |
775 |
0 |
0 |
T18 |
2005 |
1992 |
0 |
0 |
T25 |
1914 |
1902 |
0 |
0 |
T26 |
684 |
651 |
0 |
0 |
T27 |
2400 |
2333 |
0 |
0 |
T28 |
2059 |
2005 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
230255580 |
229176436 |
0 |
0 |
T1 |
95894 |
95875 |
0 |
0 |
T4 |
23321 |
12968 |
0 |
0 |
T5 |
51249 |
51203 |
0 |
0 |
T6 |
1133 |
1107 |
0 |
0 |
T7 |
807 |
775 |
0 |
0 |
T18 |
2005 |
1992 |
0 |
0 |
T25 |
1914 |
1902 |
0 |
0 |
T26 |
684 |
651 |
0 |
0 |
T27 |
2400 |
2333 |
0 |
0 |
T28 |
2059 |
2005 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 8 | 8 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
6 |
6 |
Assert Coverage for Instance : tb.dut.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165512981 |
0 |
2415 |
T1 |
189793 |
189698 |
0 |
3 |
T4 |
46157 |
4148 |
0 |
3 |
T5 |
25623 |
25570 |
0 |
3 |
T6 |
1165 |
1081 |
0 |
3 |
T7 |
1633 |
1466 |
0 |
3 |
T18 |
2047 |
1990 |
0 |
3 |
T25 |
838 |
811 |
0 |
3 |
T26 |
1411 |
1269 |
0 |
3 |
T27 |
1249 |
1190 |
0 |
3 |
T28 |
2059 |
1975 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165512981 |
0 |
2415 |
T1 |
189793 |
189698 |
0 |
3 |
T4 |
46157 |
4148 |
0 |
3 |
T5 |
25623 |
25570 |
0 |
3 |
T6 |
1165 |
1081 |
0 |
3 |
T7 |
1633 |
1466 |
0 |
3 |
T18 |
2047 |
1990 |
0 |
3 |
T25 |
838 |
811 |
0 |
3 |
T26 |
1411 |
1269 |
0 |
3 |
T27 |
1249 |
1190 |
0 |
3 |
T28 |
2059 |
1975 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165512981 |
0 |
2415 |
T1 |
189793 |
189698 |
0 |
3 |
T4 |
46157 |
4148 |
0 |
3 |
T5 |
25623 |
25570 |
0 |
3 |
T6 |
1165 |
1081 |
0 |
3 |
T7 |
1633 |
1466 |
0 |
3 |
T18 |
2047 |
1990 |
0 |
3 |
T25 |
838 |
811 |
0 |
3 |
T26 |
1411 |
1269 |
0 |
3 |
T27 |
1249 |
1190 |
0 |
3 |
T28 |
2059 |
1975 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165512981 |
0 |
2415 |
T1 |
189793 |
189698 |
0 |
3 |
T4 |
46157 |
4148 |
0 |
3 |
T5 |
25623 |
25570 |
0 |
3 |
T6 |
1165 |
1081 |
0 |
3 |
T7 |
1633 |
1466 |
0 |
3 |
T18 |
2047 |
1990 |
0 |
3 |
T25 |
838 |
811 |
0 |
3 |
T26 |
1411 |
1269 |
0 |
3 |
T27 |
1249 |
1190 |
0 |
3 |
T28 |
2059 |
1975 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165512981 |
0 |
2415 |
T1 |
189793 |
189698 |
0 |
3 |
T4 |
46157 |
4148 |
0 |
3 |
T5 |
25623 |
25570 |
0 |
3 |
T6 |
1165 |
1081 |
0 |
3 |
T7 |
1633 |
1466 |
0 |
3 |
T18 |
2047 |
1990 |
0 |
3 |
T25 |
838 |
811 |
0 |
3 |
T26 |
1411 |
1269 |
0 |
3 |
T27 |
1249 |
1190 |
0 |
3 |
T28 |
2059 |
1975 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
124 |
1 |
1 |
128 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
gen_flops.gen_no_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165512981 |
0 |
2415 |
T1 |
189793 |
189698 |
0 |
3 |
T4 |
46157 |
4148 |
0 |
3 |
T5 |
25623 |
25570 |
0 |
3 |
T6 |
1165 |
1081 |
0 |
3 |
T7 |
1633 |
1466 |
0 |
3 |
T18 |
2047 |
1990 |
0 |
3 |
T25 |
838 |
811 |
0 |
3 |
T26 |
1411 |
1269 |
0 |
3 |
T27 |
1249 |
1190 |
0 |
3 |
T28 |
2059 |
1975 |
0 |
3 |
Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
165520087 |
0 |
0 |
T1 |
189793 |
189701 |
0 |
0 |
T4 |
46157 |
4169 |
0 |
0 |
T5 |
25623 |
25573 |
0 |
0 |
T6 |
1165 |
1084 |
0 |
0 |
T7 |
1633 |
1469 |
0 |
0 |
T18 |
2047 |
1993 |
0 |
0 |
T25 |
838 |
814 |
0 |
0 |
T26 |
1411 |
1272 |
0 |
0 |
T27 |
1249 |
1193 |
0 |
0 |
T28 |
2059 |
1978 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474941902 |
0 |
0 |
T1 |
199776 |
199679 |
0 |
0 |
T4 |
48584 |
4387 |
0 |
0 |
T5 |
106768 |
106556 |
0 |
0 |
T6 |
2367 |
2198 |
0 |
0 |
T7 |
1683 |
1514 |
0 |
0 |
T18 |
4178 |
4066 |
0 |
0 |
T25 |
3987 |
3875 |
0 |
0 |
T26 |
1425 |
1284 |
0 |
0 |
T27 |
5000 |
4774 |
0 |
0 |
T28 |
4288 |
4119 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474934939 |
0 |
2415 |
T1 |
199776 |
199676 |
0 |
3 |
T4 |
48584 |
4366 |
0 |
3 |
T5 |
106768 |
106553 |
0 |
3 |
T6 |
2367 |
2195 |
0 |
3 |
T7 |
1683 |
1511 |
0 |
3 |
T18 |
4178 |
4063 |
0 |
3 |
T25 |
3987 |
3872 |
0 |
3 |
T26 |
1425 |
1281 |
0 |
3 |
T27 |
5000 |
4771 |
0 |
3 |
T28 |
4288 |
4116 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
33261 |
0 |
0 |
T1 |
199776 |
1 |
0 |
0 |
T4 |
48584 |
7 |
0 |
0 |
T5 |
106768 |
1 |
0 |
0 |
T6 |
2367 |
5 |
0 |
0 |
T7 |
1683 |
12 |
0 |
0 |
T18 |
4178 |
26 |
0 |
0 |
T25 |
3987 |
16 |
0 |
0 |
T26 |
1425 |
3 |
0 |
0 |
T27 |
5000 |
4 |
0 |
0 |
T28 |
4288 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474941902 |
0 |
0 |
T1 |
199776 |
199679 |
0 |
0 |
T4 |
48584 |
4387 |
0 |
0 |
T5 |
106768 |
106556 |
0 |
0 |
T6 |
2367 |
2198 |
0 |
0 |
T7 |
1683 |
1514 |
0 |
0 |
T18 |
4178 |
4066 |
0 |
0 |
T25 |
3987 |
3875 |
0 |
0 |
T26 |
1425 |
1284 |
0 |
0 |
T27 |
5000 |
4774 |
0 |
0 |
T28 |
4288 |
4119 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474941902 |
0 |
0 |
T1 |
199776 |
199679 |
0 |
0 |
T4 |
48584 |
4387 |
0 |
0 |
T5 |
106768 |
106556 |
0 |
0 |
T6 |
2367 |
2198 |
0 |
0 |
T7 |
1683 |
1514 |
0 |
0 |
T18 |
4178 |
4066 |
0 |
0 |
T25 |
3987 |
3875 |
0 |
0 |
T26 |
1425 |
1284 |
0 |
0 |
T27 |
5000 |
4774 |
0 |
0 |
T28 |
4288 |
4119 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474941902 |
0 |
0 |
T1 |
199776 |
199679 |
0 |
0 |
T4 |
48584 |
4387 |
0 |
0 |
T5 |
106768 |
106556 |
0 |
0 |
T6 |
2367 |
2198 |
0 |
0 |
T7 |
1683 |
1514 |
0 |
0 |
T18 |
4178 |
4066 |
0 |
0 |
T25 |
3987 |
3875 |
0 |
0 |
T26 |
1425 |
1284 |
0 |
0 |
T27 |
5000 |
4774 |
0 |
0 |
T28 |
4288 |
4119 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474934939 |
0 |
2415 |
T1 |
199776 |
199676 |
0 |
3 |
T4 |
48584 |
4366 |
0 |
3 |
T5 |
106768 |
106553 |
0 |
3 |
T6 |
2367 |
2195 |
0 |
3 |
T7 |
1683 |
1511 |
0 |
3 |
T18 |
4178 |
4063 |
0 |
3 |
T25 |
3987 |
3872 |
0 |
3 |
T26 |
1425 |
1281 |
0 |
3 |
T27 |
5000 |
4771 |
0 |
3 |
T28 |
4288 |
4116 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
33114 |
0 |
0 |
T1 |
199776 |
1 |
0 |
0 |
T4 |
48584 |
7 |
0 |
0 |
T5 |
106768 |
1 |
0 |
0 |
T6 |
2367 |
1 |
0 |
0 |
T7 |
1683 |
6 |
0 |
0 |
T18 |
4178 |
26 |
0 |
0 |
T25 |
3987 |
9 |
0 |
0 |
T26 |
1425 |
5 |
0 |
0 |
T27 |
5000 |
4 |
0 |
0 |
T28 |
4288 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474941902 |
0 |
0 |
T1 |
199776 |
199679 |
0 |
0 |
T4 |
48584 |
4387 |
0 |
0 |
T5 |
106768 |
106556 |
0 |
0 |
T6 |
2367 |
2198 |
0 |
0 |
T7 |
1683 |
1514 |
0 |
0 |
T18 |
4178 |
4066 |
0 |
0 |
T25 |
3987 |
3875 |
0 |
0 |
T26 |
1425 |
1284 |
0 |
0 |
T27 |
5000 |
4774 |
0 |
0 |
T28 |
4288 |
4119 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474941902 |
0 |
0 |
T1 |
199776 |
199679 |
0 |
0 |
T4 |
48584 |
4387 |
0 |
0 |
T5 |
106768 |
106556 |
0 |
0 |
T6 |
2367 |
2198 |
0 |
0 |
T7 |
1683 |
1514 |
0 |
0 |
T18 |
4178 |
4066 |
0 |
0 |
T25 |
3987 |
3875 |
0 |
0 |
T26 |
1425 |
1284 |
0 |
0 |
T27 |
5000 |
4774 |
0 |
0 |
T28 |
4288 |
4119 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474941902 |
0 |
0 |
T1 |
199776 |
199679 |
0 |
0 |
T4 |
48584 |
4387 |
0 |
0 |
T5 |
106768 |
106556 |
0 |
0 |
T6 |
2367 |
2198 |
0 |
0 |
T7 |
1683 |
1514 |
0 |
0 |
T18 |
4178 |
4066 |
0 |
0 |
T25 |
3987 |
3875 |
0 |
0 |
T26 |
1425 |
1284 |
0 |
0 |
T27 |
5000 |
4774 |
0 |
0 |
T28 |
4288 |
4119 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474934939 |
0 |
2415 |
T1 |
199776 |
199676 |
0 |
3 |
T4 |
48584 |
4366 |
0 |
3 |
T5 |
106768 |
106553 |
0 |
3 |
T6 |
2367 |
2195 |
0 |
3 |
T7 |
1683 |
1511 |
0 |
3 |
T18 |
4178 |
4063 |
0 |
3 |
T25 |
3987 |
3872 |
0 |
3 |
T26 |
1425 |
1281 |
0 |
3 |
T27 |
5000 |
4771 |
0 |
3 |
T28 |
4288 |
4116 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
33520 |
0 |
0 |
T1 |
199776 |
1 |
0 |
0 |
T4 |
48584 |
7 |
0 |
0 |
T5 |
106768 |
1 |
0 |
0 |
T6 |
2367 |
9 |
0 |
0 |
T7 |
1683 |
6 |
0 |
0 |
T18 |
4178 |
27 |
0 |
0 |
T25 |
3987 |
18 |
0 |
0 |
T26 |
1425 |
5 |
0 |
0 |
T27 |
5000 |
4 |
0 |
0 |
T28 |
4288 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474941902 |
0 |
0 |
T1 |
199776 |
199679 |
0 |
0 |
T4 |
48584 |
4387 |
0 |
0 |
T5 |
106768 |
106556 |
0 |
0 |
T6 |
2367 |
2198 |
0 |
0 |
T7 |
1683 |
1514 |
0 |
0 |
T18 |
4178 |
4066 |
0 |
0 |
T25 |
3987 |
3875 |
0 |
0 |
T26 |
1425 |
1284 |
0 |
0 |
T27 |
5000 |
4774 |
0 |
0 |
T28 |
4288 |
4119 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474941902 |
0 |
0 |
T1 |
199776 |
199679 |
0 |
0 |
T4 |
48584 |
4387 |
0 |
0 |
T5 |
106768 |
106556 |
0 |
0 |
T6 |
2367 |
2198 |
0 |
0 |
T7 |
1683 |
1514 |
0 |
0 |
T18 |
4178 |
4066 |
0 |
0 |
T25 |
3987 |
3875 |
0 |
0 |
T26 |
1425 |
1284 |
0 |
0 |
T27 |
5000 |
4774 |
0 |
0 |
T28 |
4288 |
4119 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 6 | 6 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
CONT_ASSIGN | 96 | 1 | 1 | 100.00 |
ALWAYS | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
96 |
4 |
4 |
117 |
1 |
1 |
168 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Total | Covered | Percent |
Conditions | 8 | 8 | 100.00 |
Logical | 8 | 8 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
LINE 96
EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
--------------------------------1--------------------------------
-1- | Status | Tests |
0 | Covered | T6,T4,T7 |
1 | Covered | T6,T4,T7 |
Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
TERNARY |
96 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
LineNo. Expression
-1-: 96 ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T6,T4,T7 |
0 |
Covered |
T6,T4,T7 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474941902 |
0 |
0 |
T1 |
199776 |
199679 |
0 |
0 |
T4 |
48584 |
4387 |
0 |
0 |
T5 |
106768 |
106556 |
0 |
0 |
T6 |
2367 |
2198 |
0 |
0 |
T7 |
1683 |
1514 |
0 |
0 |
T18 |
4178 |
4066 |
0 |
0 |
T25 |
3987 |
3875 |
0 |
0 |
T26 |
1425 |
1284 |
0 |
0 |
T27 |
5000 |
4774 |
0 |
0 |
T28 |
4288 |
4119 |
0 |
0 |
gen_flops.gen_stable_chks.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474934939 |
0 |
2415 |
T1 |
199776 |
199676 |
0 |
3 |
T4 |
48584 |
4366 |
0 |
3 |
T5 |
106768 |
106553 |
0 |
3 |
T6 |
2367 |
2195 |
0 |
3 |
T7 |
1683 |
1511 |
0 |
3 |
T18 |
4178 |
4063 |
0 |
3 |
T25 |
3987 |
3872 |
0 |
3 |
T26 |
1425 |
1281 |
0 |
3 |
T27 |
5000 |
4771 |
0 |
3 |
T28 |
4288 |
4116 |
0 |
3 |
gen_flops.gen_stable_chks.OutputIfUnstable_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
33219 |
0 |
0 |
T1 |
199776 |
1 |
0 |
0 |
T4 |
48584 |
7 |
0 |
0 |
T5 |
106768 |
1 |
0 |
0 |
T6 |
2367 |
5 |
0 |
0 |
T7 |
1683 |
18 |
0 |
0 |
T18 |
4178 |
26 |
0 |
0 |
T25 |
3987 |
18 |
0 |
0 |
T26 |
1425 |
1 |
0 |
0 |
T27 |
5000 |
4 |
0 |
0 |
T28 |
4288 |
4 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
145 |
|
unreachable |
146 |
|
unreachable |
148 |
|
unreachable |
155 |
1 |
1 |
168 |
1 |
1 |
Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync
Assertion Details
NumCopiesMustBeGreaterZero_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
805 |
805 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T18 |
1 |
1 |
0 |
0 |
T25 |
1 |
1 |
0 |
0 |
T26 |
1 |
1 |
0 |
0 |
T27 |
1 |
1 |
0 |
0 |
T28 |
1 |
1 |
0 |
0 |
OutputsKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474941902 |
0 |
0 |
T1 |
199776 |
199679 |
0 |
0 |
T4 |
48584 |
4387 |
0 |
0 |
T5 |
106768 |
106556 |
0 |
0 |
T6 |
2367 |
2198 |
0 |
0 |
T7 |
1683 |
1514 |
0 |
0 |
T18 |
4178 |
4066 |
0 |
0 |
T25 |
3987 |
3875 |
0 |
0 |
T26 |
1425 |
1284 |
0 |
0 |
T27 |
5000 |
4774 |
0 |
0 |
T28 |
4288 |
4119 |
0 |
0 |
gen_no_flops.OutputDelay_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
479501481 |
474941902 |
0 |
0 |
T1 |
199776 |
199679 |
0 |
0 |
T4 |
48584 |
4387 |
0 |
0 |
T5 |
106768 |
106556 |
0 |
0 |
T6 |
2367 |
2198 |
0 |
0 |
T7 |
1683 |
1514 |
0 |
0 |
T18 |
4178 |
4066 |
0 |
0 |
T25 |
3987 |
3875 |
0 |
0 |
T26 |
1425 |
1284 |
0 |
0 |
T27 |
5000 |
4774 |
0 |
0 |
T28 |
4288 |
4119 |
0 |
0 |