Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T6,T4,T7
0	1	Unreachable
1	0	Covered	T4,T2,T3

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	167999125	165374587	0	0
AllClkBypReqTrue_A	167999125	143187	0	0
IoClkBypReqFalse_A	167999125	165286910	0	2415
IoClkBypReqTrue_A	167999125	226238	0	0
LcClkBypAckFalse_A	167999125	165383648	0	0
LcClkBypAckTrue_A	167999125	134126	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	165374587	0	0
T1	189793	189700	0	0
T4	46157	4162	0	0
T5	25623	25572	0	0
T6	1165	1083	0	0
T7	1633	1468	0	0
T18	2047	1992	0	0
T25	838	813	0	0
T26	1411	1179	0	0
T27	1249	1192	0	0
T28	2059	1977	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	143187	0	0
T1	189793	0	0	0
T2	186725	578	0	0
T3	0	288	0	0
T12	0	734	0	0
T13	0	481	0	0
T18	2047	0	0	0
T19	2686	95	0	0
T20	127004	0	0	0
T21	1410	0	0	0
T22	931	0	0	0
T26	1411	92	0	0
T27	1249	0	0	0
T28	2059	0	0	0
T31	0	312	0	0
T54	0	315	0	0
T117	0	73	0	0
T118	0	172	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	165286910	0	2415
T1	189793	189698	0	3
T4	46157	4148	0	3
T5	25623	25570	0	3
T6	1165	1081	0	3
T7	1633	1466	0	3
T18	2047	1990	0	3
T25	838	811	0	3
T26	1411	1179	0	3
T27	1249	1190	0	3
T28	2059	1975	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	226238	0	0
T1	189793	0	0	0
T2	186725	975	0	0
T3	0	557	0	0
T12	0	1146	0	0
T13	0	679	0	0
T18	2047	0	0	0
T19	2686	528	0	0
T20	127004	0	0	0
T21	1410	0	0	0
T22	931	0	0	0
T26	1411	90	0	0
T27	1249	0	0	0
T28	2059	0	0	0
T31	0	309	0	0
T54	0	548	0	0
T56	0	29	0	0
T118	0	115	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	165383648	0	0
T1	189793	189700	0	0
T4	46157	4162	0	0
T5	25623	25572	0	0
T6	1165	1083	0	0
T7	1633	1468	0	0
T18	2047	1992	0	0
T25	838	813	0	0
T26	1411	1194	0	0
T27	1249	1192	0	0
T28	2059	1977	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	134126	0	0
T1	189793	0	0	0
T2	186725	672	0	0
T3	0	339	0	0
T12	0	723	0	0
T13	0	463	0	0
T18	2047	0	0	0
T19	2686	231	0	0
T20	127004	0	0	0
T21	1410	0	0	0
T22	931	0	0	0
T26	1411	77	0	0
T27	1249	0	0	0
T28	2059	0	0	0
T31	0	276	0	0
T54	0	345	0	0
T118	0	69	0	0
T119	0	58	0	0