Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1918007760	15480	0	0
TransStop_A	1918007760	7848	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1918007760	15480	0	0
T1	799104	0	0	0
T2	2978000	62	0	0
T3	0	78	0	0
T12	0	53	0	0
T18	16712	18	0	0
T19	10960	0	0	0
T20	510740	0	0	0
T21	5644	0	0	0
T22	18640	3	0	0
T23	6120	0	0	0
T24	0	13	0	0
T27	20004	4	0	0
T28	17152	4	0	0
T31	0	89	0	0
T120	0	9	0	0
T121	0	27	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1918007760	7848	0	0
T1	799104	0	0	0
T2	2978000	32	0	0
T3	0	45	0	0
T12	0	107	0	0
T18	16712	8	0	0
T19	10960	0	0	0
T20	510740	0	0	0
T21	5644	0	0	0
T22	18640	0	0	0
T23	6120	0	0	0
T24	0	2	0	0
T27	20004	4	0	0
T28	17152	4	0	0
T31	0	52	0	0
T55	0	1	0	0
T120	0	7	0	0
T121	0	10	0	0
T122	0	14	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	479501940	3870	0	0
TransStop_A	479501940	1971	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501940	3870	0	0
T1	199776	0	0	0
T2	744500	16	0	0
T3	0	18	0	0
T12	0	53	0	0
T18	4178	6	0	0
T19	2740	0	0	0
T20	127685	0	0	0
T21	1411	0	0	0
T22	4660	0	0	0
T23	1530	0	0	0
T24	0	1	0	0
T27	5001	1	0	0
T28	4288	1	0	0
T31	0	28	0	0
T120	0	3	0	0
T121	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501940	1971	0	0
T1	199776	0	0	0
T2	744500	8	0	0
T3	0	13	0	0
T12	0	27	0	0
T18	4178	3	0	0
T19	2740	0	0	0
T20	127685	0	0	0
T21	1411	0	0	0
T22	4660	0	0	0
T23	1530	0	0	0
T27	5001	1	0	0
T28	4288	1	0	0
T31	0	15	0	0
T120	0	3	0	0
T121	0	4	0	0
T122	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	479501940	3819	0	0
TransStop_A	479501940	1937	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501940	3819	0	0
T1	199776	0	0	0
T2	744500	10	0	0
T3	0	21	0	0
T18	4178	4	0	0
T19	2740	0	0	0
T20	127685	0	0	0
T21	1411	0	0	0
T22	4660	1	0	0
T23	1530	0	0	0
T24	0	3	0	0
T27	5001	1	0	0
T28	4288	1	0	0
T31	0	22	0	0
T120	0	3	0	0
T121	0	4	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501940	1937	0	0
T1	199776	0	0	0
T2	744500	4	0	0
T3	0	11	0	0
T12	0	32	0	0
T18	4178	3	0	0
T19	2740	0	0	0
T20	127685	0	0	0
T21	1411	0	0	0
T22	4660	0	0	0
T23	1530	0	0	0
T27	5001	1	0	0
T28	4288	1	0	0
T31	0	12	0	0
T120	0	3	0	0
T121	0	3	0	0
T122	0	6	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	479501940	3874	0	0
TransStop_A	479501940	1965	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501940	3874	0	0
T1	199776	0	0	0
T2	744500	19	0	0
T3	0	20	0	0
T18	4178	4	0	0
T19	2740	0	0	0
T20	127685	0	0	0
T21	1411	0	0	0
T22	4660	1	0	0
T23	1530	0	0	0
T24	0	5	0	0
T27	5001	1	0	0
T28	4288	1	0	0
T31	0	21	0	0
T120	0	2	0	0
T121	0	8	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501940	1965	0	0
T1	199776	0	0	0
T2	744500	10	0	0
T3	0	10	0	0
T12	0	21	0	0
T18	4178	2	0	0
T19	2740	0	0	0
T20	127685	0	0	0
T21	1411	0	0	0
T22	4660	0	0	0
T23	1530	0	0	0
T24	0	1	0	0
T27	5001	1	0	0
T28	4288	1	0	0
T31	0	14	0	0
T120	0	1	0	0
T121	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	479501940	3917	0	0
TransStop_A	479501940	1975	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501940	3917	0	0
T1	199776	0	0	0
T2	744500	17	0	0
T3	0	19	0	0
T18	4178	4	0	0
T19	2740	0	0	0
T20	127685	0	0	0
T21	1411	0	0	0
T22	4660	1	0	0
T23	1530	0	0	0
T24	0	4	0	0
T27	5001	1	0	0
T28	4288	1	0	0
T31	0	18	0	0
T120	0	1	0	0
T121	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501940	1975	0	0
T1	199776	0	0	0
T2	744500	10	0	0
T3	0	11	0	0
T12	0	27	0	0
T18	4178	0	0	0
T19	2740	0	0	0
T20	127685	0	0	0
T21	1411	0	0	0
T22	4660	0	0	0
T23	1530	0	0	0
T24	0	1	0	0
T27	5001	1	0	0
T28	4288	1	0	0
T31	0	11	0	0
T55	0	1	0	0
T121	0	1	0	0
T122	0	4	0	0