Unified Coverage Report :: Module :: clkmgr_lost_calib_regwen_sva_if

Module : clkmgr_lost_calib_regwen_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_regwen_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_regwen_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_regwen_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_lost_calib_regwen_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
RegwenOff_A	167999125	15420994	0	54

RegwenOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	15420994	0	54
T1	189793	35477	0	1
T2	186725	329089	0	0
T3	0	50322	0	0
T5	25623	637	0	1
T11	0	6994	0	1
T12	0	67321	0	0
T13	0	26065	0	0
T14	0	6949	0	1
T15	0	25370	0	0
T16	0	10469	0	0
T18	2047	0	0	0
T19	2686	0	0	0
T20	127004	0	0	0
T21	1410	0	0	0
T26	1411	0	0	0
T27	1249	0	0	0
T28	2059	0	0	0
T29	0	0	0	1
T86	0	0	0	1
T123	0	0	0	1
T124	0	0	0	1
T125	0	0	0	1
T126	0	0	0	1