Line Coverage for Module :
clkmgr_extclk_sva_if
| Line No. | Total | Covered | Percent |
TOTAL | | 3 | 3 | 100.00 |
ALWAYS | 34 | 1 | 1 | 100.00 |
ALWAYS | 49 | 1 | 1 | 100.00 |
ALWAYS | 66 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
49 |
1 |
1 |
66 |
1 |
1 |
Cond Coverage for Module :
clkmgr_extclk_sva_if
| Total | Covered | Percent |
Conditions | 19 | 19 | 100.00 |
Logical | 19 | 19 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 34
EXPRESSION (lc_clk_byp_req_i == On)
------------1-----------
-1- | Status | Tests |
0 | Covered | T26,T19,T2 |
1 | Covered | T26,T19,T2 |
LINE 49
EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (lc_hw_debug_en_i == On))
---------------1-------------- ------------2-----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T26,T19,T2 |
1 | 0 | Covered | T19,T2,T3 |
1 | 1 | Covered | T26,T19,T2 |
LINE 49
SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T26,T19,T2 |
1 | Covered | T26,T19,T2 |
LINE 49
SUB-EXPRESSION (lc_hw_debug_en_i == On)
------------1-----------
-1- | Status | Tests |
0 | Covered | T19,T2,T3 |
1 | Covered | T26,T19,T2 |
LINE 66
EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (extclk_ctrl_hi_speed_sel == MuBi4True) && (lc_hw_debug_en_i == On))
---------------1-------------- -------------------2------------------- ------------3-----------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T2,T3,T12 |
1 | 0 | 1 | Covered | T26,T2,T3 |
1 | 1 | 0 | Covered | T19,T2,T3 |
1 | 1 | 1 | Covered | T26,T19,T2 |
LINE 66
SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
---------------1--------------
-1- | Status | Tests |
0 | Covered | T4,T26,T19 |
1 | Covered | T26,T19,T2 |
LINE 66
SUB-EXPRESSION (extclk_ctrl_hi_speed_sel == MuBi4True)
-------------------1-------------------
-1- | Status | Tests |
0 | Covered | T4,T26,T19 |
1 | Covered | T4,T26,T19 |
LINE 66
SUB-EXPRESSION (lc_hw_debug_en_i == On)
------------1-----------
-1- | Status | Tests |
0 | Covered | T4,T19,T2 |
1 | Covered | T26,T19,T2 |
Assert Coverage for Module :
clkmgr_extclk_sva_if
Assertion Details
AllClkBypReqFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
4419 |
0 |
0 |
T1 |
189793 |
0 |
0 |
0 |
T2 |
186725 |
13 |
0 |
0 |
T3 |
0 |
16 |
0 |
0 |
T12 |
0 |
33 |
0 |
0 |
T13 |
0 |
19 |
0 |
0 |
T18 |
2047 |
0 |
0 |
0 |
T19 |
2686 |
2 |
0 |
0 |
T20 |
127004 |
0 |
0 |
0 |
T21 |
1410 |
0 |
0 |
0 |
T22 |
931 |
0 |
0 |
0 |
T26 |
1411 |
2 |
0 |
0 |
T27 |
1249 |
0 |
0 |
0 |
T28 |
2059 |
0 |
0 |
0 |
T31 |
0 |
12 |
0 |
0 |
T54 |
0 |
9 |
0 |
0 |
T117 |
0 |
3 |
0 |
0 |
T118 |
0 |
5 |
0 |
0 |
AllClkBypReqRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
4419 |
0 |
0 |
T1 |
189793 |
0 |
0 |
0 |
T2 |
186725 |
13 |
0 |
0 |
T3 |
0 |
16 |
0 |
0 |
T12 |
0 |
33 |
0 |
0 |
T13 |
0 |
19 |
0 |
0 |
T18 |
2047 |
0 |
0 |
0 |
T19 |
2686 |
2 |
0 |
0 |
T20 |
127004 |
0 |
0 |
0 |
T21 |
1410 |
0 |
0 |
0 |
T22 |
931 |
0 |
0 |
0 |
T26 |
1411 |
2 |
0 |
0 |
T27 |
1249 |
0 |
0 |
0 |
T28 |
2059 |
0 |
0 |
0 |
T31 |
0 |
12 |
0 |
0 |
T54 |
0 |
9 |
0 |
0 |
T117 |
0 |
3 |
0 |
0 |
T118 |
0 |
5 |
0 |
0 |
HiSpeedSelFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
2633 |
0 |
0 |
T1 |
189793 |
0 |
0 |
0 |
T2 |
186725 |
5 |
0 |
0 |
T3 |
0 |
11 |
0 |
0 |
T12 |
0 |
13 |
0 |
0 |
T13 |
0 |
9 |
0 |
0 |
T18 |
2047 |
0 |
0 |
0 |
T19 |
2686 |
2 |
0 |
0 |
T20 |
127004 |
0 |
0 |
0 |
T21 |
1410 |
0 |
0 |
0 |
T22 |
931 |
0 |
0 |
0 |
T26 |
1411 |
1 |
0 |
0 |
T27 |
1249 |
0 |
0 |
0 |
T28 |
2059 |
0 |
0 |
0 |
T31 |
0 |
8 |
0 |
0 |
T54 |
0 |
5 |
0 |
0 |
T117 |
0 |
3 |
0 |
0 |
T118 |
0 |
4 |
0 |
0 |
HiSpeedSelRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
2633 |
0 |
0 |
T1 |
189793 |
0 |
0 |
0 |
T2 |
186725 |
5 |
0 |
0 |
T3 |
0 |
11 |
0 |
0 |
T12 |
0 |
13 |
0 |
0 |
T13 |
0 |
9 |
0 |
0 |
T18 |
2047 |
0 |
0 |
0 |
T19 |
2686 |
2 |
0 |
0 |
T20 |
127004 |
0 |
0 |
0 |
T21 |
1410 |
0 |
0 |
0 |
T22 |
931 |
0 |
0 |
0 |
T26 |
1411 |
1 |
0 |
0 |
T27 |
1249 |
0 |
0 |
0 |
T28 |
2059 |
0 |
0 |
0 |
T31 |
0 |
8 |
0 |
0 |
T54 |
0 |
5 |
0 |
0 |
T117 |
0 |
3 |
0 |
0 |
T118 |
0 |
4 |
0 |
0 |
IoClkBypReqFall_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
5505 |
0 |
0 |
T1 |
189793 |
0 |
0 |
0 |
T2 |
186725 |
21 |
0 |
0 |
T3 |
0 |
21 |
0 |
0 |
T12 |
0 |
37 |
0 |
0 |
T13 |
0 |
21 |
0 |
0 |
T18 |
2047 |
0 |
0 |
0 |
T19 |
2686 |
11 |
0 |
0 |
T20 |
127004 |
0 |
0 |
0 |
T21 |
1410 |
0 |
0 |
0 |
T22 |
931 |
0 |
0 |
0 |
T26 |
1411 |
2 |
0 |
0 |
T27 |
1249 |
0 |
0 |
0 |
T28 |
2059 |
0 |
0 |
0 |
T31 |
0 |
9 |
0 |
0 |
T54 |
0 |
13 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T118 |
0 |
3 |
0 |
0 |
IoClkBypReqRise_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
167999125 |
5505 |
0 |
0 |
T1 |
189793 |
0 |
0 |
0 |
T2 |
186725 |
21 |
0 |
0 |
T3 |
0 |
21 |
0 |
0 |
T12 |
0 |
37 |
0 |
0 |
T13 |
0 |
21 |
0 |
0 |
T18 |
2047 |
0 |
0 |
0 |
T19 |
2686 |
11 |
0 |
0 |
T20 |
127004 |
0 |
0 |
0 |
T21 |
1410 |
0 |
0 |
0 |
T22 |
931 |
0 |
0 |
0 |
T26 |
1411 |
2 |
0 |
0 |
T27 |
1249 |
0 |
0 |
0 |
T28 |
2059 |
0 |
0 |
0 |
T31 |
0 |
9 |
0 |
0 |
T54 |
0 |
13 |
0 |
0 |
T56 |
0 |
1 |
0 |
0 |
T118 |
0 |
3 |
0 |
0 |