Module Definition
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Module : clkmgr_extclk_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_extclk_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_extclk_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : clkmgr_extclk_sva_if
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS3411100.00
ALWAYS4911100.00
ALWAYS6611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_extclk_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
49 1 1
66 1 1


Cond Coverage for Module : clkmgr_extclk_sva_if
TotalCoveredPercent
Conditions1919100.00
Logical1919100.00
Non-Logical00
Event00

 LINE       34
 EXPRESSION (lc_clk_byp_req_i == On)
            ------------1-----------
-1-StatusTests
0CoveredT26,T19,T2
1CoveredT26,T19,T2

 LINE       49
 EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (lc_hw_debug_en_i == On))
             ---------------1--------------    ------------2-----------
-1--2-StatusTests
01CoveredT26,T19,T2
10CoveredT19,T2,T3
11CoveredT26,T19,T2

 LINE       49
 SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
                ---------------1--------------
-1-StatusTests
0CoveredT26,T19,T2
1CoveredT26,T19,T2

 LINE       49
 SUB-EXPRESSION (lc_hw_debug_en_i == On)
                ------------1-----------
-1-StatusTests
0CoveredT19,T2,T3
1CoveredT26,T19,T2

 LINE       66
 EXPRESSION ((extclk_ctrl_sel == MuBi4True) && (extclk_ctrl_hi_speed_sel == MuBi4True) && (lc_hw_debug_en_i == On))
             ---------------1--------------    -------------------2-------------------    ------------3-----------
-1--2--3-StatusTests
011CoveredT2,T3,T12
101CoveredT26,T2,T3
110CoveredT19,T2,T3
111CoveredT26,T19,T2

 LINE       66
 SUB-EXPRESSION (extclk_ctrl_sel == MuBi4True)
                ---------------1--------------
-1-StatusTests
0CoveredT4,T26,T19
1CoveredT26,T19,T2

 LINE       66
 SUB-EXPRESSION (extclk_ctrl_hi_speed_sel == MuBi4True)
                -------------------1-------------------
-1-StatusTests
0CoveredT4,T26,T19
1CoveredT4,T26,T19

 LINE       66
 SUB-EXPRESSION (lc_hw_debug_en_i == On)
                ------------1-----------
-1-StatusTests
0CoveredT4,T19,T2
1CoveredT26,T19,T2

Assert Coverage for Module : clkmgr_extclk_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AllClkBypReqFall_A 167999125 4419 0 0
AllClkBypReqRise_A 167999125 4419 0 0
HiSpeedSelFall_A 167999125 2633 0 0
HiSpeedSelRise_A 167999125 2633 0 0
IoClkBypReqFall_A 167999125 5505 0 0
IoClkBypReqRise_A 167999125 5505 0 0


AllClkBypReqFall_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 167999125 4419 0 0
T1 189793 0 0 0
T2 186725 13 0 0
T3 0 16 0 0
T12 0 33 0 0
T13 0 19 0 0
T18 2047 0 0 0
T19 2686 2 0 0
T20 127004 0 0 0
T21 1410 0 0 0
T22 931 0 0 0
T26 1411 2 0 0
T27 1249 0 0 0
T28 2059 0 0 0
T31 0 12 0 0
T54 0 9 0 0
T117 0 3 0 0
T118 0 5 0 0

AllClkBypReqRise_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 167999125 4419 0 0
T1 189793 0 0 0
T2 186725 13 0 0
T3 0 16 0 0
T12 0 33 0 0
T13 0 19 0 0
T18 2047 0 0 0
T19 2686 2 0 0
T20 127004 0 0 0
T21 1410 0 0 0
T22 931 0 0 0
T26 1411 2 0 0
T27 1249 0 0 0
T28 2059 0 0 0
T31 0 12 0 0
T54 0 9 0 0
T117 0 3 0 0
T118 0 5 0 0

HiSpeedSelFall_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 167999125 2633 0 0
T1 189793 0 0 0
T2 186725 5 0 0
T3 0 11 0 0
T12 0 13 0 0
T13 0 9 0 0
T18 2047 0 0 0
T19 2686 2 0 0
T20 127004 0 0 0
T21 1410 0 0 0
T22 931 0 0 0
T26 1411 1 0 0
T27 1249 0 0 0
T28 2059 0 0 0
T31 0 8 0 0
T54 0 5 0 0
T117 0 3 0 0
T118 0 4 0 0

HiSpeedSelRise_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 167999125 2633 0 0
T1 189793 0 0 0
T2 186725 5 0 0
T3 0 11 0 0
T12 0 13 0 0
T13 0 9 0 0
T18 2047 0 0 0
T19 2686 2 0 0
T20 127004 0 0 0
T21 1410 0 0 0
T22 931 0 0 0
T26 1411 1 0 0
T27 1249 0 0 0
T28 2059 0 0 0
T31 0 8 0 0
T54 0 5 0 0
T117 0 3 0 0
T118 0 4 0 0

IoClkBypReqFall_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 167999125 5505 0 0
T1 189793 0 0 0
T2 186725 21 0 0
T3 0 21 0 0
T12 0 37 0 0
T13 0 21 0 0
T18 2047 0 0 0
T19 2686 11 0 0
T20 127004 0 0 0
T21 1410 0 0 0
T22 931 0 0 0
T26 1411 2 0 0
T27 1249 0 0 0
T28 2059 0 0 0
T31 0 9 0 0
T54 0 13 0 0
T56 0 1 0 0
T118 0 3 0 0

IoClkBypReqRise_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 167999125 5505 0 0
T1 189793 0 0 0
T2 186725 21 0 0
T3 0 21 0 0
T12 0 37 0 0
T13 0 21 0 0
T18 2047 0 0 0
T19 2686 11 0 0
T20 127004 0 0 0
T21 1410 0 0 0
T22 931 0 0 0
T26 1411 2 0 0
T27 1249 0 0 0
T28 2059 0 0 0
T31 0 9 0 0
T54 0 13 0 0
T56 0 1 0 0
T118 0 3 0 0

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