Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	168913009	5163008	0	0
clk_enables_rd_A	168913009	51593	0	0
clk_hints_rd_A	168913009	46901	0	0
extclk_ctrl_rd_A	168913009	58610	0	0
extclk_ctrl_regwen_rd_A	168913009	45035	0	0
jitter_enable_rd_A	168913009	61009	0	0
jitter_regwen_rd_A	168913009	50077	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168913009	5163008	0	0
T2	186725	66624	0	0
T3	555362	0	0	0
T11	35907	0	0	0
T12	0	79247	0	0
T17	0	122187	0	0
T20	127004	0	0	0
T21	1410	0	0	0
T22	931	0	0	0
T23	1669	0	0	0
T24	1573	0	0	0
T30	232260	0	0	0
T34	0	30570	0	0
T37	1323	0	0	0
T68	0	76318	0	0
T69	0	131094	0	0
T70	0	127676	0	0
T71	0	163630	0	0
T72	0	130586	0	0
T73	0	54728	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168913009	51593	0	0
T1	189793	0	0	0
T2	186725	0	0	0
T3	555362	0	0	0
T16	0	19	0	0
T18	2047	0	0	0
T19	2686	0	0	0
T20	127004	0	0	0
T21	1410	0	0	0
T22	931	0	0	0
T23	1669	0	0	0
T28	2059	3	0	0
T34	0	944	0	0
T69	0	5059	0	0
T72	0	4668	0	0
T147	0	6	0	0
T148	0	5	0	0
T149	0	3	0	0
T150	0	9	0	0
T151	0	4	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168913009	46901	0	0
T1	189793	0	0	0
T2	186725	0	0	0
T3	555362	0	0	0
T16	0	24	0	0
T18	2047	0	0	0
T19	2686	0	0	0
T20	127004	0	0	0
T21	1410	0	0	0
T22	931	0	0	0
T23	1669	0	0	0
T28	2059	4	0	0
T69	0	4613	0	0
T72	0	4521	0	0
T147	0	5	0	0
T148	0	2	0	0
T149	0	4	0	0
T150	0	6	0	0
T152	0	4	0	0
T153	0	3	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168913009	58610	0	0
T1	189793	0	0	0
T4	46157	44	0	0
T5	25623	0	0	0
T7	1633	0	0	0
T18	2047	0	0	0
T19	2686	76	0	0
T25	838	0	0	0
T26	1411	5	0	0
T27	1249	0	0	0
T28	2059	0	0	0
T54	0	32	0	0
T117	0	19	0	0
T118	0	30	0	0
T154	0	41	0	0
T155	0	40	0	0
T156	0	1	0	0
T157	0	58	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168913009	45035	0	0
T1	189793	0	0	0
T4	46157	12	0	0
T5	25623	0	0	0
T7	1633	0	0	0
T18	2047	0	0	0
T19	2686	0	0	0
T25	838	0	0	0
T26	1411	0	0	0
T27	1249	0	0	0
T28	2059	0	0	0
T34	0	1067	0	0
T35	0	1919	0	0
T36	0	3691	0	0
T69	0	4343	0	0
T72	0	4367	0	0
T115	0	57	0	0
T158	0	54	0	0
T159	0	1203	0	0
T160	0	4727	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168913009	61009	0	0
T1	189793	0	0	0
T2	186725	0	0	0
T3	555362	0	0	0
T16	0	535	0	0
T18	2047	0	0	0
T19	2686	0	0	0
T20	127004	0	0	0
T21	1410	0	0	0
T22	931	0	0	0
T23	1669	0	0	0
T28	2059	58	0	0
T69	0	6460	0	0
T72	0	5261	0	0
T126	0	69	0	0
T147	0	102	0	0
T148	0	130	0	0
T149	0	102	0	0
T152	0	94	0	0
T153	0	89	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168913009	50077	0	0
T34	0	1134	0	0
T35	0	2325	0	0
T36	0	4116	0	0
T69	459537	4849	0	0
T72	0	4762	0	0
T107	12368	0	0	0
T124	16732	0	0	0
T125	207427	0	0	0
T153	2370	0	0	0
T159	0	1260	0	0
T160	0	5331	0	0
T161	0	3082	0	0
T162	0	2308	0	0
T163	0	3369	0	0
T164	757	0	0	0
T165	843462	0	0	0
T166	897781	0	0	0
T167	1491	0	0	0
T168	14507	0	0	0