Unified Coverage Report :: Module :: clkmgr_div_sva_if

Module : clkmgr_div_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_div2_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_div4_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Module : clkmgr_div_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T25
1	0	Covered	T19,T2,T3
1	1	Covered	T26,T19,T2

---

Assert Coverage for Module : clkmgr_div_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	449598295	4705	0	0
g_div2.Div2Whole_A	449598295	5596	0	0
g_div4.Div4Stepped_A	224002575	4611	0	0
g_div4.Div4Whole_A	224002575	5292	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449598295	4705	0	0
T1	191779	0	0	0
T2	708937	19	0	0
T3	0	13	0	0
T12	0	32	0	0
T13	0	16	0	0
T18	4010	0	0	0
T19	2630	5	0	0
T20	93774	0	0	0
T21	1355	0	0	0
T22	4473	0	0	0
T26	1368	2	0	0
T27	4800	0	0	0
T28	4117	0	0	0
T31	0	13	0	0
T54	0	10	0	0
T117	0	2	0	0
T118	0	3	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449598295	5596	0	0
T1	191779	0	0	0
T2	708937	20	0	0
T3	0	21	0	0
T12	0	40	0	0
T18	4010	0	0	0
T19	2630	9	0	0
T20	93774	0	0	0
T21	1355	0	0	0
T22	4473	0	0	0
T26	1368	2	0	0
T27	4800	0	0	0
T28	4117	0	0	0
T31	0	14	0	0
T54	0	12	0	0
T56	0	1	0	0
T117	0	3	0	0
T118	0	3	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224002575	4611	0	0
T1	95871	0	0	0
T2	354500	19	0	0
T3	0	11	0	0
T12	0	32	0	0
T13	0	16	0	0
T18	1993	0	0	0
T19	1421	5	0	0
T20	46834	0	0	0
T21	645	0	0	0
T22	2197	0	0	0
T26	693	2	0	0
T27	2333	0	0	0
T28	2006	0	0	0
T31	0	13	0	0
T54	0	10	0	0
T117	0	1	0	0
T118	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224002575	5292	0	0
T1	95871	0	0	0
T2	354500	20	0	0
T3	0	16	0	0
T12	0	39	0	0
T13	0	19	0	0
T18	1993	0	0	0
T19	1421	7	0	0
T20	46834	0	0	0
T21	645	0	0	0
T22	2197	0	0	0
T26	693	2	0	0
T27	2333	0	0	0
T28	2006	0	0	0
T31	0	14	0	0
T54	0	12	0	0
T117	0	2	0	0
T118	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T25
1	0	Covered	T19,T2,T3
1	1	Covered	T26,T19,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div2.Div2Stepped_A	449598295	4705	0	0
g_div2.Div2Whole_A	449598295	5596	0	0

g_div2.Div2Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449598295	4705	0	0
T1	191779	0	0	0
T2	708937	19	0	0
T3	0	13	0	0
T12	0	32	0	0
T13	0	16	0	0
T18	4010	0	0	0
T19	2630	5	0	0
T20	93774	0	0	0
T21	1355	0	0	0
T22	4473	0	0	0
T26	1368	2	0	0
T27	4800	0	0	0
T28	4117	0	0	0
T31	0	13	0	0
T54	0	10	0	0
T117	0	2	0	0
T118	0	3	0	0

g_div2.Div2Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449598295	5596	0	0
T1	191779	0	0	0
T2	708937	20	0	0
T3	0	21	0	0
T12	0	40	0	0
T18	4010	0	0	0
T19	2630	9	0	0
T20	93774	0	0	0
T21	1355	0	0	0
T22	4473	0	0	0
T26	1368	2	0	0
T27	4800	0	0	0
T28	4117	0	0	0
T31	0	14	0	0
T54	0	12	0	0
T56	0	1	0	0
T117	0	3	0	0
T118	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	25	1	1	100.00
ALWAYS	28	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
25	1	1
28	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T7,T25
1	0	Covered	T19,T2,T3
1	1	Covered	T26,T19,T2

---

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
g_div4.Div4Stepped_A	224002575	4611	0	0
g_div4.Div4Whole_A	224002575	5292	0	0

g_div4.Div4Stepped_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224002575	4611	0	0
T1	95871	0	0	0
T2	354500	19	0	0
T3	0	11	0	0
T12	0	32	0	0
T13	0	16	0	0
T18	1993	0	0	0
T19	1421	5	0	0
T20	46834	0	0	0
T21	645	0	0	0
T22	2197	0	0	0
T26	693	2	0	0
T27	2333	0	0	0
T28	2006	0	0	0
T31	0	13	0	0
T54	0	10	0	0
T117	0	1	0	0
T118	0	3	0	0

g_div4.Div4Whole_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224002575	5292	0	0
T1	95871	0	0	0
T2	354500	20	0	0
T3	0	16	0	0
T12	0	39	0	0
T13	0	19	0	0
T18	1993	0	0	0
T19	1421	7	0	0
T20	46834	0	0	0
T21	645	0	0	0
T22	2197	0	0	0
T26	693	2	0	0
T27	2333	0	0	0
T28	2006	0	0	0
T31	0	14	0	0
T54	0	12	0	0
T117	0	2	0	0
T118	0	3	0	0