Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	503997375	444	0	0
StatusRise_A	503997375	444	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503997375	444	0	0
T1	569379	0	0	0
T4	138471	0	0	0
T5	76869	0	0	0
T6	3495	4	0	0
T7	4899	0	0	0
T18	6141	0	0	0
T23	0	13	0	0
T25	2514	0	0	0
T26	4233	0	0	0
T27	3747	0	0	0
T28	6177	0	0	0
T37	0	15	0	0
T164	0	8	0	0
T169	0	3	0	0
T170	0	4	0	0
T171	0	3	0	0
T172	0	12	0	0
T173	0	13	0	0
T174	0	5	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	503997375	444	0	0
T1	569379	0	0	0
T4	138471	0	0	0
T5	76869	0	0	0
T6	3495	4	0	0
T7	4899	0	0	0
T18	6141	0	0	0
T23	0	13	0	0
T25	2514	0	0	0
T26	4233	0	0	0
T27	3747	0	0	0
T28	6177	0	0	0
T37	0	15	0	0
T164	0	8	0	0
T169	0	3	0	0
T170	0	4	0	0
T171	0	3	0	0
T172	0	12	0	0
T173	0	13	0	0
T174	0	5	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	167999125	150	0	0
StatusRise_A	167999125	150	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	150	0	0
T1	189793	0	0	0
T4	46157	0	0	0
T5	25623	0	0	0
T6	1165	2	0	0
T7	1633	0	0	0
T18	2047	0	0	0
T23	0	5	0	0
T25	838	0	0	0
T26	1411	0	0	0
T27	1249	0	0	0
T28	2059	0	0	0
T37	0	6	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	4	0	0
T173	0	6	0	0
T174	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	150	0	0
T1	189793	0	0	0
T4	46157	0	0	0
T5	25623	0	0	0
T6	1165	2	0	0
T7	1633	0	0	0
T18	2047	0	0	0
T23	0	5	0	0
T25	838	0	0	0
T26	1411	0	0	0
T27	1249	0	0	0
T28	2059	0	0	0
T37	0	6	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	4	0	0
T173	0	6	0	0
T174	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	167999125	151	0	0
StatusRise_A	167999125	151	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	151	0	0
T1	189793	0	0	0
T4	46157	0	0	0
T5	25623	0	0	0
T6	1165	1	0	0
T7	1633	0	0	0
T18	2047	0	0	0
T23	0	3	0	0
T25	838	0	0	0
T26	1411	0	0	0
T27	1249	0	0	0
T28	2059	0	0	0
T37	0	5	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	151	0	0
T1	189793	0	0	0
T4	46157	0	0	0
T5	25623	0	0	0
T6	1165	1	0	0
T7	1633	0	0	0
T18	2047	0	0	0
T23	0	3	0	0
T25	838	0	0	0
T26	1411	0	0	0
T27	1249	0	0	0
T28	2059	0	0	0
T37	0	5	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	167999125	143	0	0
StatusRise_A	167999125	143	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	143	0	0
T1	189793	0	0	0
T4	46157	0	0	0
T5	25623	0	0	0
T6	1165	1	0	0
T7	1633	0	0	0
T18	2047	0	0	0
T23	0	5	0	0
T25	838	0	0	0
T26	1411	0	0	0
T27	1249	0	0	0
T28	2059	0	0	0
T37	0	4	0	0
T164	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	5	0	0
T173	0	4	0	0
T174	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	167999125	143	0	0
T1	189793	0	0	0
T4	46157	0	0	0
T5	25623	0	0	0
T6	1165	1	0	0
T7	1633	0	0	0
T18	2047	0	0	0
T23	0	5	0	0
T25	838	0	0	0
T26	1411	0	0	0
T27	1249	0	0	0
T28	2059	0	0	0
T37	0	4	0	0
T164	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	5	0	0
T173	0	4	0	0
T174	0	2	0	0