Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T2
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	48548	0	0
CgEnOn_A	2147483647	39289	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	48548	0	0
T1	2157484	3	0	0
T2	0	16	0	0
T3	0	18	0	0
T4	483302	21	0	0
T5	1152896	3	0	0
T6	25612	13	0	0
T7	18040	24	0	0
T18	45068	9	0	0
T23	0	20	0	0
T25	43014	41	0	0
T26	15422	3	0	0
T27	53730	7	0	0
T28	46102	7	0	0
T37	0	31	0	0
T164	0	15	0	0
T169	0	5	0	0
T170	0	10	0	0
T171	0	5	0	0
T172	0	15	0	0
T173	0	15	0	0
T174	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	39289	0	0
T1	2157484	0	0	0
T2	0	154	0	0
T3	0	76	0	0
T4	483302	0	0	0
T5	1152896	0	0	0
T6	25612	12	0	0
T7	18040	21	0	0
T18	45068	10	0	0
T22	0	1	0	0
T23	0	34	0	0
T24	0	4	0	0
T25	43014	38	0	0
T26	15422	0	0	0
T27	53730	5	0	0
T28	46102	5	0	0
T31	0	42	0	0
T37	0	52	0	0
T120	0	3	0	0
T164	0	15	0	0
T169	0	5	0	0
T170	0	10	0	0
T171	0	5	0	0
T172	0	15	0	0
T173	0	15	0	0
T174	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T2
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	224002167	156	0	0
CgEnOn_A	224002167	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224002167	156	0	0
T1	95871	0	0	0
T4	12969	0	0	0
T5	51201	0	0	0
T6	1130	1	0	0
T7	775	0	0	0
T18	1993	0	0	0
T23	0	3	0	0
T25	1902	0	0	0
T26	692	0	0	0
T27	2333	0	0	0
T28	2005	0	0	0
T37	0	5	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224002167	156	0	0
T1	95871	0	0	0
T4	12969	0	0	0
T5	51201	0	0	0
T6	1130	1	0	0
T7	775	0	0	0
T18	1993	0	0	0
T23	0	3	0	0
T25	1902	0	0	0
T26	692	0	0	0
T27	2333	0	0	0
T28	2005	0	0	0
T37	0	5	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T2
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	112000421	156	0	0
CgEnOn_A	112000421	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112000421	156	0	0
T1	47935	0	0	0
T4	6485	0	0	0
T5	25600	0	0	0
T6	565	1	0	0
T7	387	0	0	0
T18	996	0	0	0
T23	0	3	0	0
T25	951	0	0	0
T26	346	0	0	0
T27	1166	0	0	0
T28	1003	0	0	0
T37	0	5	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112000421	156	0	0
T1	47935	0	0	0
T4	6485	0	0	0
T5	25600	0	0	0
T6	565	1	0	0
T7	387	0	0	0
T18	996	0	0	0
T23	0	3	0	0
T25	951	0	0	0
T26	346	0	0	0
T27	1166	0	0	0
T28	1003	0	0	0
T37	0	5	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T2
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	112000421	156	0	0
CgEnOn_A	112000421	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112000421	156	0	0
T1	47935	0	0	0
T4	6485	0	0	0
T5	25600	0	0	0
T6	565	1	0	0
T7	387	0	0	0
T18	996	0	0	0
T23	0	3	0	0
T25	951	0	0	0
T26	346	0	0	0
T27	1166	0	0	0
T28	1003	0	0	0
T37	0	5	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112000421	156	0	0
T1	47935	0	0	0
T4	6485	0	0	0
T5	25600	0	0	0
T6	565	1	0	0
T7	387	0	0	0
T18	996	0	0	0
T23	0	3	0	0
T25	951	0	0	0
T26	346	0	0	0
T27	1166	0	0	0
T28	1003	0	0	0
T37	0	5	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T2
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	112000421	156	0	0
CgEnOn_A	112000421	156	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112000421	156	0	0
T1	47935	0	0	0
T4	6485	0	0	0
T5	25600	0	0	0
T6	565	1	0	0
T7	387	0	0	0
T18	996	0	0	0
T23	0	3	0	0
T25	951	0	0	0
T26	346	0	0	0
T27	1166	0	0	0
T28	1003	0	0	0
T37	0	5	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112000421	156	0	0
T1	47935	0	0	0
T4	6485	0	0	0
T5	25600	0	0	0
T6	565	1	0	0
T7	387	0	0	0
T18	996	0	0	0
T23	0	3	0	0
T25	951	0	0	0
T26	346	0	0	0
T27	1166	0	0	0
T28	1003	0	0	0
T37	0	5	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T2
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	449597862	156	0	0
CgEnOn_A	449597862	152	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449597862	156	0	0
T1	191779	0	0	0
T4	46639	0	0	0
T5	102494	0	0	0
T6	2312	1	0	0
T7	1615	0	0	0
T18	4010	0	0	0
T23	0	3	0	0
T25	3828	0	0	0
T26	1368	0	0	0
T27	4800	0	0	0
T28	4117	0	0	0
T37	0	5	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449597862	152	0	0
T1	191779	0	0	0
T4	46639	0	0	0
T5	102494	0	0	0
T6	2312	1	0	0
T7	1615	0	0	0
T18	4010	0	0	0
T23	0	3	0	0
T25	3828	0	0	0
T26	1368	0	0	0
T27	4800	0	0	0
T28	4117	0	0	0
T37	0	5	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	3	0	0
T173	0	3	0	0
T174	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T2
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	479501481	153	0	0
CgEnOn_A	479501481	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501481	153	0	0
T1	199776	0	0	0
T4	48584	0	0	0
T5	106768	0	0	0
T6	2367	2	0	0
T7	1683	0	0	0
T18	4178	0	0	0
T23	0	5	0	0
T25	3987	0	0	0
T26	1425	0	0	0
T27	5000	0	0	0
T28	4288	0	0	0
T37	0	6	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	4	0	0
T173	0	6	0	0
T174	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501481	151	0	0
T1	199776	0	0	0
T4	48584	0	0	0
T5	106768	0	0	0
T6	2367	2	0	0
T7	1683	0	0	0
T18	4178	0	0	0
T23	0	5	0	0
T25	3987	0	0	0
T26	1425	0	0	0
T27	5000	0	0	0
T28	4288	0	0	0
T37	0	6	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	4	0	0
T173	0	6	0	0
T174	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T2
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	479501481	153	0	0
CgEnOn_A	479501481	151	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501481	153	0	0
T1	199776	0	0	0
T4	48584	0	0	0
T5	106768	0	0	0
T6	2367	2	0	0
T7	1683	0	0	0
T18	4178	0	0	0
T23	0	5	0	0
T25	3987	0	0	0
T26	1425	0	0	0
T27	5000	0	0	0
T28	4288	0	0	0
T37	0	6	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	4	0	0
T173	0	6	0	0
T174	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501481	151	0	0
T1	199776	0	0	0
T4	48584	0	0	0
T5	106768	0	0	0
T6	2367	2	0	0
T7	1683	0	0	0
T18	4178	0	0	0
T23	0	5	0	0
T25	3987	0	0	0
T26	1425	0	0	0
T27	5000	0	0	0
T28	4288	0	0	0
T37	0	6	0	0
T164	0	3	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	4	0	0
T173	0	6	0	0
T174	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T2
1	0	Unreachable
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	230255580	145	0	0
CgEnOn_A	230255580	143	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230255580	145	0	0
T1	95894	0	0	0
T4	23321	0	0	0
T5	51249	0	0	0
T6	1133	1	0	0
T7	807	0	0	0
T17	0	1	0	0
T18	2005	0	0	0
T23	0	5	0	0
T25	1914	0	0	0
T26	684	0	0	0
T27	2400	0	0	0
T28	2059	0	0	0
T37	0	4	0	0
T164	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	5	0	0
T173	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230255580	143	0	0
T1	95894	0	0	0
T4	23321	0	0	0
T5	51249	0	0	0
T6	1133	1	0	0
T7	807	0	0	0
T18	2005	0	0	0
T23	0	5	0	0
T25	1914	0	0	0
T26	684	0	0	0
T27	2400	0	0	0
T28	2059	0	0	0
T37	0	4	0	0
T164	0	2	0	0
T169	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	5	0	0
T173	0	4	0	0
T174	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T23,T37
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	112000421	7751	0	0
CgEnOn_A	112000421	5443	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112000421	7751	0	0
T1	47935	1	0	0
T4	6485	7	0	0
T5	25600	1	0	0
T6	565	2	0	0
T7	387	7	0	0
T18	996	1	0	0
T25	951	14	0	0
T26	346	1	0	0
T27	1166	2	0	0
T28	1003	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	112000421	5443	0	0
T1	47935	0	0	0
T2	0	43	0	0
T3	0	12	0	0
T4	6485	0	0	0
T5	25600	0	0	0
T6	565	1	0	0
T7	387	6	0	0
T18	996	0	0	0
T23	0	3	0	0
T25	951	13	0	0
T26	346	0	0	0
T27	1166	1	0	0
T28	1003	1	0	0
T31	0	14	0	0
T37	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T23,T37
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	224002167	7816	0	0
CgEnOn_A	224002167	5508	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224002167	7816	0	0
T1	95871	1	0	0
T4	12969	7	0	0
T5	51201	1	0	0
T6	1130	2	0	0
T7	775	8	0	0
T18	1993	1	0	0
T25	1902	13	0	0
T26	692	1	0	0
T27	2333	2	0	0
T28	2005	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224002167	5508	0	0
T1	95871	0	0	0
T2	0	43	0	0
T3	0	12	0	0
T4	12969	0	0	0
T5	51201	0	0	0
T6	1130	1	0	0
T7	775	7	0	0
T18	1993	0	0	0
T23	0	3	0	0
T25	1902	12	0	0
T26	692	0	0	0
T27	2333	1	0	0
T28	2005	1	0	0
T31	0	15	0	0
T37	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T23,T37
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	449597862	7844	0	0
CgEnOn_A	449597862	5532	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449597862	7844	0	0
T1	191779	1	0	0
T4	46639	7	0	0
T5	102494	1	0	0
T6	2312	2	0	0
T7	1615	9	0	0
T18	4010	1	0	0
T25	3828	14	0	0
T26	1368	1	0	0
T27	4800	2	0	0
T28	4117	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	449597862	5532	0	0
T1	191779	0	0	0
T2	0	42	0	0
T3	0	13	0	0
T4	46639	0	0	0
T5	102494	0	0	0
T6	2312	1	0	0
T7	1615	8	0	0
T18	4010	0	0	0
T23	0	3	0	0
T25	3828	13	0	0
T26	1368	0	0	0
T27	4800	1	0	0
T28	4117	1	0	0
T31	0	13	0	0
T37	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T23,T37
1	0	Covered	T6,T4,T7
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	230255580	7814	0	0
CgEnOn_A	230255580	5501	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230255580	7814	0	0
T1	95894	1	0	0
T4	23321	7	0	0
T5	51249	1	0	0
T6	1133	2	0	0
T7	807	8	0	0
T18	2005	1	0	0
T25	1914	15	0	0
T26	684	1	0	0
T27	2400	2	0	0
T28	2059	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	230255580	5501	0	0
T1	95894	0	0	0
T2	0	41	0	0
T3	0	9	0	0
T4	23321	0	0	0
T5	51249	0	0	0
T6	1133	1	0	0
T7	807	7	0	0
T18	2005	0	0	0
T23	0	5	0	0
T25	1914	14	0	0
T26	684	0	0	0
T27	2400	1	0	0
T28	2059	1	0	0
T31	0	15	0	0
T37	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T2
1	0	Covered	T27,T28,T18
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	479501481	4023	0	0
CgEnOn_A	479501481	4021	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501481	4023	0	0
T1	199776	0	0	0
T2	0	16	0	0
T3	0	18	0	0
T4	48584	0	0	0
T5	106768	0	0	0
T6	2367	2	0	0
T7	1683	0	0	0
T18	4178	6	0	0
T23	0	5	0	0
T24	0	1	0	0
T25	3987	0	0	0
T26	1425	0	0	0
T27	5000	1	0	0
T28	4288	1	0	0
T37	0	6	0	0
T120	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501481	4021	0	0
T1	199776	0	0	0
T2	0	16	0	0
T3	0	18	0	0
T4	48584	0	0	0
T5	106768	0	0	0
T6	2367	2	0	0
T7	1683	0	0	0
T18	4178	6	0	0
T23	0	5	0	0
T24	0	1	0	0
T25	3987	0	0	0
T26	1425	0	0	0
T27	5000	1	0	0
T28	4288	1	0	0
T37	0	6	0	0
T120	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T2
1	0	Covered	T27,T28,T18
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	479501481	3972	0	0
CgEnOn_A	479501481	3970	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501481	3972	0	0
T1	199776	0	0	0
T2	0	10	0	0
T3	0	21	0	0
T4	48584	0	0	0
T5	106768	0	0	0
T6	2367	2	0	0
T7	1683	0	0	0
T18	4178	4	0	0
T22	0	1	0	0
T23	0	5	0	0
T24	0	3	0	0
T25	3987	0	0	0
T26	1425	0	0	0
T27	5000	1	0	0
T28	4288	1	0	0
T37	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501481	3970	0	0
T1	199776	0	0	0
T2	0	10	0	0
T3	0	21	0	0
T4	48584	0	0	0
T5	106768	0	0	0
T6	2367	2	0	0
T7	1683	0	0	0
T18	4178	4	0	0
T22	0	1	0	0
T23	0	5	0	0
T24	0	3	0	0
T25	3987	0	0	0
T26	1425	0	0	0
T27	5000	1	0	0
T28	4288	1	0	0
T37	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T2
1	0	Covered	T27,T28,T18
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	479501481	4027	0	0
CgEnOn_A	479501481	4025	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501481	4027	0	0
T1	199776	0	0	0
T2	0	19	0	0
T3	0	20	0	0
T4	48584	0	0	0
T5	106768	0	0	0
T6	2367	2	0	0
T7	1683	0	0	0
T18	4178	4	0	0
T22	0	1	0	0
T23	0	5	0	0
T24	0	5	0	0
T25	3987	0	0	0
T26	1425	0	0	0
T27	5000	1	0	0
T28	4288	1	0	0
T37	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501481	4025	0	0
T1	199776	0	0	0
T2	0	19	0	0
T3	0	20	0	0
T4	48584	0	0	0
T5	106768	0	0	0
T6	2367	2	0	0
T7	1683	0	0	0
T18	4178	4	0	0
T22	0	1	0	0
T23	0	5	0	0
T24	0	5	0	0
T25	3987	0	0	0
T26	1425	0	0	0
T27	5000	1	0	0
T28	4288	1	0	0
T37	0	6	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T6,T4,T2
1	0	Covered	T27,T28,T18
1	1	Covered	T6,T4,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	479501481	4070	0	0
CgEnOn_A	479501481	4068	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501481	4070	0	0
T1	199776	0	0	0
T2	0	17	0	0
T3	0	19	0	0
T4	48584	0	0	0
T5	106768	0	0	0
T6	2367	2	0	0
T7	1683	0	0	0
T18	4178	4	0	0
T22	0	1	0	0
T23	0	5	0	0
T24	0	4	0	0
T25	3987	0	0	0
T26	1425	0	0	0
T27	5000	1	0	0
T28	4288	1	0	0
T37	0	6	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	479501481	4068	0	0
T1	199776	0	0	0
T2	0	17	0	0
T3	0	19	0	0
T4	48584	0	0	0
T5	106768	0	0	0
T6	2367	2	0	0
T7	1683	0	0	0
T18	4178	4	0	0
T22	0	1	0	0
T23	0	5	0	0
T24	0	4	0	0
T25	3987	0	0	0
T26	1425	0	0	0
T27	5000	1	0	0
T28	4288	1	0	0
T37	0	6	0	0