Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	589913	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3299852

1

T5

54

T6

1

T7

53

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	957055	1			T5	80		T6	2		T7	76
values[0x0]	1349621	1			T5	37		T6	2		T7	33
values[0x1]	1583089	1			T5	23		T6	3		T7	24

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	328671	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

3561094

1

T5

61

T6

1

T7

68

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15789	1			T2	538		T20	1		T21	1
valid_sources[0x01]	15494	1			T1	3		T2	6		T4	1
valid_sources[0x02]	14789	1			T1	1		T2	279		T20	1
valid_sources[0x03]	14751	1			T7	2		T1	2		T2	708
valid_sources[0x04]	14614	1			T1	6		T2	1		T19	7
valid_sources[0x05]	14478	1			T1	2		T2	218		T21	1
valid_sources[0x06]	15828	1			T1	4		T2	1152		T4	3
valid_sources[0x07]	14990	1			T1	7		T2	94		T20	1
valid_sources[0x08]	14886	1			T1	1		T2	308		T19	1
valid_sources[0x09]	15613	1			T7	1		T1	3		T2	480
valid_sources[0x0a]	14554	1			T1	4		T2	132		T4	2
valid_sources[0x0b]	16074	1			T1	1		T2	564		T4	1
valid_sources[0x0c]	14414	1			T1	1		T2	8		T4	1
valid_sources[0x0d]	15257	1			T7	1		T1	4		T2	488
valid_sources[0x0e]	14947	1			T1	3		T2	59		T20	1
valid_sources[0x0f]	13477	1			T2	480		T3	632		T28	7
valid_sources[0x10]	14168	1			T1	2		T2	21		T4	1
valid_sources[0x11]	16977	1			T1	2		T2	176		T4	2
valid_sources[0x12]	16131	1			T7	1		T1	3		T2	514
valid_sources[0x13]	15007	1			T1	1		T2	12		T20	1
valid_sources[0x14]	15706	1			T1	3		T2	553		T24	6
valid_sources[0x15]	16399	1			T1	1		T2	525		T20	1
valid_sources[0x16]	15119	1			T1	1		T2	109		T3	92
valid_sources[0x17]	14499	1			T1	4		T2	50		T23	1
valid_sources[0x18]	18389	1			T1	1		T2	1382		T24	5
valid_sources[0x19]	16717	1			T1	5		T2	1103		T20	1
valid_sources[0x1a]	16304	1			T7	1		T1	1		T2	199
valid_sources[0x1b]	14731	1			T1	2		T2	367		T4	4
valid_sources[0x1c]	14453	1			T1	3		T2	471		T4	1
valid_sources[0x1d]	15203	1			T7	1		T1	1		T2	594
valid_sources[0x1e]	16095	1			T1	3		T2	156		T4	1
valid_sources[0x1f]	13381	1			T1	2		T2	148		T4	2
valid_sources[0x20]	16913	1			T1	3		T2	570		T4	2
valid_sources[0x21]	14440	1			T1	1		T2	66		T24	1
valid_sources[0x22]	13117	1			T2	38		T4	3		T24	4
valid_sources[0x23]	16623	1			T1	4		T2	50		T19	2
valid_sources[0x24]	15847	1			T7	1		T1	2		T2	122
valid_sources[0x25]	14263	1			T7	1		T1	3		T2	296
valid_sources[0x26]	15846	1			T1	2		T2	379		T4	3
valid_sources[0x27]	16151	1			T1	3		T2	324		T4	4
valid_sources[0x28]	15377	1			T7	1		T1	3		T2	138
valid_sources[0x29]	16094	1			T1	2		T2	993		T4	6
valid_sources[0x2a]	13568	1			T1	2		T2	134		T4	2
valid_sources[0x2b]	15855	1			T1	2		T2	737		T24	7
valid_sources[0x2c]	13934	1			T1	4		T2	262		T19	1
valid_sources[0x2d]	15742	1			T7	2		T1	2		T2	637
valid_sources[0x2e]	14613	1			T1	2		T2	84		T24	3
valid_sources[0x2f]	15368	1			T1	3		T2	550		T4	2
valid_sources[0x30]	14672	1			T1	2		T2	726		T4	1
valid_sources[0x31]	15166	1			T7	1		T1	2		T2	5
valid_sources[0x32]	14691	1			T7	2		T2	543		T4	2
valid_sources[0x33]	15845	1			T2	720		T19	2		T24	1
valid_sources[0x34]	15521	1			T7	2		T1	2		T2	300
valid_sources[0x35]	14847	1			T1	2		T2	855		T24	7
valid_sources[0x36]	14378	1			T1	2		T2	115		T19	2
valid_sources[0x37]	14851	1			T1	3		T2	157		T19	1
valid_sources[0x38]	16792	1			T7	2		T1	1		T2	292
valid_sources[0x39]	15053	1			T7	1		T1	4		T2	393
valid_sources[0x3a]	15085	1			T7	1		T2	448		T4	3
valid_sources[0x3b]	15699	1			T7	1		T1	1		T2	327
valid_sources[0x3c]	16431	1			T1	4		T2	608		T3	712
valid_sources[0x3d]	15482	1			T1	2		T2	212		T4	1
valid_sources[0x3e]	15721	1			T1	4		T2	954		T4	3
valid_sources[0x3f]	14294	1			T1	1		T2	506		T4	1
valid_sources[0x40]	14189	1			T1	1		T2	501		T4	2
valid_sources[0x41]	17573	1			T7	3		T1	1		T2	265
valid_sources[0x42]	15294	1			T1	1		T2	337		T4	3
valid_sources[0x43]	15691	1			T7	1		T1	1		T2	151
valid_sources[0x44]	15884	1			T7	1		T1	2		T2	402
valid_sources[0x45]	14149	1			T2	422		T4	1		T24	4
valid_sources[0x46]	14942	1			T1	1		T2	99		T21	2
valid_sources[0x47]	14699	1			T7	1		T1	4		T2	136
valid_sources[0x48]	17075	1			T1	4		T2	40		T4	1
valid_sources[0x49]	15397	1			T1	4		T2	517		T4	3
valid_sources[0x4a]	16988	1			T1	2		T2	431		T4	1
valid_sources[0x4b]	15751	1			T1	2		T2	548		T4	2
valid_sources[0x4c]	15695	1			T7	1		T1	1		T2	440
valid_sources[0x4d]	15880	1			T1	4		T2	441		T4	1
valid_sources[0x4e]	14982	1			T7	2		T1	2		T2	825
valid_sources[0x4f]	13972	1			T7	3		T1	2		T2	9
valid_sources[0x50]	14423	1			T1	1		T2	322		T4	2
valid_sources[0x51]	16613	1			T2	846		T4	3		T24	5
valid_sources[0x52]	14633	1			T1	2		T2	194		T20	1
valid_sources[0x53]	15787	1			T7	1		T1	3		T2	253
valid_sources[0x54]	14516	1			T7	2		T1	4		T86	1
valid_sources[0x55]	14350	1			T7	2		T1	4		T2	259
valid_sources[0x56]	15064	1			T7	1		T1	1		T2	8
valid_sources[0x57]	14954	1			T1	1		T2	295		T24	1
valid_sources[0x58]	13369	1			T1	3		T2	94		T24	1
valid_sources[0x59]	15918	1			T7	2		T1	3		T2	14
valid_sources[0x5a]	15244	1			T1	4		T2	36		T4	6
valid_sources[0x5b]	13941	1			T1	1		T2	14		T20	3
valid_sources[0x5c]	17020	1			T1	1		T2	276		T24	3
valid_sources[0x5d]	15973	1			T1	3		T2	374		T24	3
valid_sources[0x5e]	14547	1			T7	2		T1	2		T2	406
valid_sources[0x5f]	17228	1			T7	1		T1	2		T2	438
valid_sources[0x60]	14489	1			T7	3		T1	6		T2	197
valid_sources[0x61]	15218	1			T1	2		T2	809		T4	1
valid_sources[0x62]	14853	1			T1	1		T2	650		T4	1
valid_sources[0x63]	13781	1			T7	2		T1	6		T2	80
valid_sources[0x64]	14231	1			T7	1		T1	1		T2	266
valid_sources[0x65]	15588	1			T1	5		T2	238		T20	1
valid_sources[0x66]	15884	1			T7	2		T1	1		T2	132
valid_sources[0x67]	15798	1			T1	5		T2	279		T24	1
valid_sources[0x68]	14615	1			T1	1		T2	449		T24	3
valid_sources[0x69]	14531	1			T7	1		T1	2		T2	3
valid_sources[0x6a]	16055	1			T7	2		T1	4		T2	477
valid_sources[0x6b]	14731	1			T7	1		T1	1		T2	385
valid_sources[0x6c]	14631	1			T1	2		T2	232		T19	1
valid_sources[0x6d]	15577	1			T7	2		T1	4		T2	105
valid_sources[0x6e]	14836	1			T7	1		T2	1		T3	729
valid_sources[0x6f]	13177	1			T1	3		T2	144		T4	1
valid_sources[0x70]	15027	1			T7	1		T2	640		T4	3
valid_sources[0x71]	14233	1			T7	1		T1	3		T2	527
valid_sources[0x72]	15284	1			T1	1		T2	924		T4	2
valid_sources[0x73]	14270	1			T7	2		T1	3		T2	111
valid_sources[0x74]	17852	1			T1	1		T2	240		T4	1
valid_sources[0x75]	16157	1			T6	4		T7	6		T1	1
valid_sources[0x76]	14506	1			T1	3		T2	445		T4	2
valid_sources[0x77]	15186	1			T2	280		T3	176		T28	2
valid_sources[0x78]	13415	1			T7	1		T1	2		T2	201
valid_sources[0x79]	15029	1			T7	1		T1	2		T2	116
valid_sources[0x7a]	16230	1			T7	2		T1	2		T2	305
valid_sources[0x7b]	15324	1			T1	1		T2	190		T4	1
valid_sources[0x7c]	14122	1			T7	1		T1	3		T20	1
valid_sources[0x7d]	15238	1			T1	1		T2	541		T4	3
valid_sources[0x7e]	17079	1			T7	1		T1	3		T2	532
valid_sources[0x7f]	14464	1			T1	3		T2	242		T4	1
valid_sources[0x80]	16729	1			T2	34		T4	1		T24	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

832861

1

T5

40

T6

1

T7

40

values[0x0]

all_enables

biggest_size

1257536

1

T5

10

T7

12

T1

125

values[0x1]

all_enables

biggest_size

1209455

1

T5

4

T7

1

T1

64