Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T22,T38,T39
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	947646342	13541	0	0
GateOpen_A	947646342	20098	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947646342	13541	0	0
T1	386483	20	0	0
T2	1523609	296	0	0
T3	0	346	0	0
T4	118312	0	0	0
T11	0	188	0	0
T12	0	6	0	0
T17	6879	0	0	0
T18	34031	0	0	0
T19	5506	0	0	0
T20	21270	0	0	0
T21	11874	0	0	0
T22	5002	5	0	0
T23	10028	0	0	0
T38	0	15	0	0
T39	0	12	0	0
T55	0	9	0	0
T111	0	3	0	0
T161	0	7	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	947646342	20098	0	0
T1	386483	32	0	0
T2	1523609	320	0	0
T4	118312	40	0	0
T6	4788	4	0	0
T7	6867	0	0	0
T17	6879	0	0	0
T18	34031	4	0	0
T19	5506	0	0	0
T20	21270	4	0	0
T21	11874	0	0	0
T22	0	9	0	0
T23	0	4	0	0
T24	0	80	0	0
T86	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T22,T38,T39
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	104467706	3256	0	0
GateOpen_A	104467706	4895	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104467706	3256	0	0
T1	42951	4	0	0
T2	280836	71	0	0
T3	0	89	0	0
T4	8418	0	0	0
T11	0	47	0	0
T12	0	6	0	0
T17	782	0	0	0
T18	3775	0	0	0
T19	651	0	0	0
T20	2602	0	0	0
T21	1385	0	0	0
T22	545	1	0	0
T23	1194	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T55	0	2	0	0
T161	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104467706	4895	0	0
T1	42951	7	0	0
T2	280836	77	0	0
T4	8418	10	0	0
T6	540	1	0	0
T7	759	0	0	0
T17	782	0	0	0
T18	3775	1	0	0
T19	651	0	0	0
T20	2602	1	0	0
T21	1385	0	0	0
T22	0	2	0	0
T23	0	1	0	0
T24	0	20	0	0
T86	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T22,T38,T39
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	208936216	3400	0	0
GateOpen_A	208936216	5039	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208936216	3400	0	0
T1	85908	5	0	0
T2	561675	73	0	0
T3	0	87	0	0
T4	16835	0	0	0
T11	0	46	0	0
T17	1567	0	0	0
T18	7550	0	0	0
T19	1303	0	0	0
T20	5208	0	0	0
T21	2770	0	0	0
T22	1089	1	0	0
T23	2391	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T55	0	3	0	0
T111	0	1	0	0
T161	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208936216	5039	0	0
T1	85908	8	0	0
T2	561675	79	0	0
T4	16835	10	0	0
T6	1080	1	0	0
T7	1518	0	0	0
T17	1567	0	0	0
T18	7550	1	0	0
T19	1303	0	0	0
T20	5208	1	0	0
T21	2770	0	0	0
T22	0	2	0	0
T23	0	1	0	0
T24	0	20	0	0
T86	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T22,T38,T39
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	419408116	3449	0	0
GateOpen_A	419408116	5089	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419408116	3449	0	0
T1	171747	5	0	0
T2	112372	75	0	0
T3	0	86	0	0
T4	62038	0	0	0
T11	0	49	0	0
T17	3020	0	0	0
T18	15137	0	0	0
T19	2368	0	0	0
T20	8973	0	0	0
T21	5146	0	0	0
T22	2255	1	0	0
T23	4295	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T55	0	2	0	0
T111	0	1	0	0
T161	0	2	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419408116	5089	0	0
T1	171747	8	0	0
T2	112372	81	0	0
T4	62038	10	0	0
T6	2112	1	0	0
T7	3060	0	0	0
T17	3020	0	0	0
T18	15137	1	0	0
T19	2368	0	0	0
T20	8973	1	0	0
T21	5146	0	0	0
T22	0	2	0	0
T23	0	1	0	0
T24	0	20	0	0
T86	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T6,T7

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T22,T38,T39
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	214834304	3436	0	0
GateOpen_A	214834304	5075	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214834304	3436	0	0
T1	85877	6	0	0
T2	568726	77	0	0
T3	0	84	0	0
T4	31021	0	0	0
T11	0	46	0	0
T17	1510	0	0	0
T18	7569	0	0	0
T19	1184	0	0	0
T20	4487	0	0	0
T21	2573	0	0	0
T22	1113	2	0	0
T23	2148	0	0	0
T38	0	3	0	0
T39	0	3	0	0
T55	0	2	0	0
T111	0	1	0	0
T161	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214834304	5075	0	0
T1	85877	9	0	0
T2	568726	83	0	0
T4	31021	10	0	0
T6	1056	1	0	0
T7	1530	0	0	0
T17	1510	0	0	0
T18	7569	1	0	0
T19	1184	0	0	0
T20	4487	1	0	0
T21	2573	0	0	0
T22	0	3	0	0
T23	0	1	0	0
T24	0	20	0	0
T86	0	1	0	0