Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	763521135	75896	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	763521135	75896	0	0
T1	858730	189	0	0
T2	1619765	1516	0	0
T3	0	1070	0	0
T4	132480	0	0	0
T10	0	116	0	0
T11	0	750	0	0
T12	0	709	0	0
T13	0	57	0	0
T14	0	51	0	0
T15	0	783	0	0
T16	0	1889	0	0
T17	7860	0	0	0
T18	7095	0	0	0
T19	11835	0	0	0
T20	9815	0	0	0
T21	6695	0	0	0
T22	4995	0	0	0
T23	10960	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152704227	11123	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	11123	0	0
T1	171746	28	0	0
T2	323953	247	0	0
T3	0	188	0	0
T4	26496	0	0	0
T10	0	16	0	0
T11	0	120	0	0
T12	0	105	0	0
T13	0	8	0	0
T14	0	8	0	0
T15	0	104	0	0
T16	0	247	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152704227	10955	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	10955	0	0
T1	171746	24	0	0
T2	323953	235	0	0
T3	0	188	0	0
T4	26496	0	0	0
T10	0	16	0	0
T11	0	119	0	0
T12	0	91	0	0
T13	0	8	0	0
T14	0	8	0	0
T15	0	103	0	0
T16	0	241	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152704227	15321	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	15321	0	0
T1	171746	36	0	0
T2	323953	307	0	0
T3	0	214	0	0
T4	26496	0	0	0
T10	0	23	0	0
T11	0	152	0	0
T12	0	142	0	0
T13	0	13	0	0
T14	0	10	0	0
T15	0	155	0	0
T16	0	379	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152704227	15231	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	15231	0	0
T1	171746	39	0	0
T2	323953	300	0	0
T3	0	212	0	0
T4	26496	0	0	0
T10	0	23	0	0
T11	0	152	0	0
T12	0	145	0	0
T13	0	11	0	0
T14	0	11	0	0
T15	0	159	0	0
T16	0	381	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	152704227	23266	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	23266	0	0
T1	171746	62	0	0
T2	323953	427	0	0
T3	0	268	0	0
T4	26496	0	0	0
T10	0	38	0	0
T11	0	207	0	0
T12	0	226	0	0
T13	0	17	0	0
T14	0	14	0	0
T15	0	262	0	0
T16	0	641	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0