Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	152704227	150126406	0	0
AllClkBypReqTrue_A	152704227	140211	0	0
IoClkBypReqFalse_A	152704227	150042725	0	2415
IoClkBypReqTrue_A	152704227	219282	0	0
LcClkBypAckFalse_A	152704227	150137244	0	0
LcClkBypAckTrue_A	152704227	129373	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	150126406	0	0
T1	171746	170920	0	0
T2	323953	322455	0	0
T4	26496	2444	0	0
T5	3906	3766	0	0
T6	814	711	0	0
T7	2581	2478	0	0
T17	1572	1382	0	0
T18	1419	1407	0	0
T19	2367	2230	0	0
T20	1963	1657	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	140211	0	0
T1	171746	249	0	0
T2	323953	4201	0	0
T4	26496	0	0	0
T6	814	56	0	0
T7	2581	0	0	0
T17	1572	62	0	0
T18	1419	0	0	0
T19	2367	42	0	0
T20	1963	285	0	0
T21	1339	43	0	0
T23	0	122	0	0
T85	0	25	0	0
T87	0	59	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	150042725	0	2415
T1	171746	170520	0	3
T2	323953	322266	0	3
T4	26496	2424	0	3
T5	3906	3764	0	3
T6	814	731	0	3
T7	2581	2476	0	3
T17	1572	1382	0	3
T18	1419	1405	0	3
T19	2367	1666	0	3
T20	1963	1616	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	219282	0	0
T1	171746	639	0	0
T2	323953	6068	0	0
T3	0	2661	0	0
T4	26496	0	0	0
T6	814	34	0	0
T7	2581	0	0	0
T17	1572	60	0	0
T18	1419	0	0	0
T19	2367	604	0	0
T20	1963	324	0	0
T21	1339	44	0	0
T23	0	363	0	0
T87	0	334	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	150137244	0	0
T1	171746	170796	0	0
T2	323953	322509	0	0
T4	26496	2444	0	0
T5	3906	3766	0	0
T6	814	737	0	0
T7	2581	2478	0	0
T17	1572	1391	0	0
T18	1419	1407	0	0
T19	2367	2013	0	0
T20	1963	1770	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	129373	0	0
T1	171746	373	0	0
T2	323953	3652	0	0
T3	0	1460	0	0
T4	26496	0	0	0
T6	814	30	0	0
T7	2581	0	0	0
T17	1572	53	0	0
T18	1419	0	0	0
T19	2367	259	0	0
T20	1963	172	0	0
T21	1339	0	0	0
T23	0	185	0	0
T54	0	240	0	0
T87	0	245	0	0