Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	1791920940	15977	0	0
TransStop_A	1791920940	8232	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791920940	15977	0	0
T1	715636	20	0	0
T2	474888	473	0	0
T3	0	313	0	0
T4	258496	0	0	0
T5	15780	37	0	0
T6	8800	0	0	0
T7	12748	43	0	0
T17	12584	0	0	0
T18	63072	10	0	0
T19	9864	0	0	0
T20	37388	0	0	0
T58	0	25	0	0
T86	0	19	0	0
T111	0	4	0	0
T112	0	35	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1791920940	8232	0	0
T1	715636	9	0	0
T2	474888	227	0	0
T3	0	157	0	0
T4	258496	0	0	0
T5	15780	22	0	0
T6	8800	0	0	0
T7	12748	25	0	0
T17	12584	0	0	0
T18	63072	5	0	0
T19	9864	0	0	0
T20	37388	0	0	0
T58	0	11	0	0
T86	0	9	0	0
T111	0	4	0	0
T112	0	11	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	447980235	4106	0	0
TransStop_A	447980235	2098	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447980235	4106	0	0
T1	178909	4	0	0
T2	118722	116	0	0
T3	0	77	0	0
T4	64624	0	0	0
T5	3945	11	0	0
T6	2200	0	0	0
T7	3187	9	0	0
T17	3146	0	0	0
T18	15768	3	0	0
T19	2466	0	0	0
T20	9347	0	0	0
T58	0	8	0	0
T86	0	7	0	0
T111	0	1	0	0
T112	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447980235	2098	0	0
T1	178909	1	0	0
T2	118722	55	0	0
T3	0	41	0	0
T4	64624	0	0	0
T5	3945	4	0	0
T6	2200	0	0	0
T7	3187	5	0	0
T17	3146	0	0	0
T18	15768	1	0	0
T19	2466	0	0	0
T20	9347	0	0	0
T58	0	3	0	0
T86	0	3	0	0
T111	0	1	0	0
T112	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	447980235	3983	0	0
TransStop_A	447980235	2092	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447980235	3983	0	0
T1	178909	6	0	0
T2	118722	132	0	0
T3	0	83	0	0
T4	64624	0	0	0
T5	3945	12	0	0
T6	2200	0	0	0
T7	3187	12	0	0
T17	3146	0	0	0
T18	15768	3	0	0
T19	2466	0	0	0
T20	9347	0	0	0
T58	0	5	0	0
T86	0	3	0	0
T111	0	1	0	0
T112	0	7	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447980235	2092	0	0
T1	178909	3	0	0
T2	118722	65	0	0
T3	0	39	0	0
T4	64624	0	0	0
T5	3945	7	0	0
T6	2200	0	0	0
T7	3187	7	0	0
T17	3146	0	0	0
T18	15768	2	0	0
T19	2466	0	0	0
T20	9347	0	0	0
T58	0	4	0	0
T86	0	3	0	0
T111	0	1	0	0
T112	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	447980235	3919	0	0
TransStop_A	447980235	1999	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447980235	3919	0	0
T1	178909	5	0	0
T2	118722	115	0	0
T3	0	72	0	0
T4	64624	0	0	0
T5	3945	8	0	0
T6	2200	0	0	0
T7	3187	12	0	0
T17	3146	0	0	0
T18	15768	3	0	0
T19	2466	0	0	0
T20	9347	0	0	0
T58	0	5	0	0
T86	0	5	0	0
T111	0	1	0	0
T112	0	11	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447980235	1999	0	0
T1	178909	2	0	0
T2	118722	59	0	0
T3	0	40	0	0
T4	64624	0	0	0
T5	3945	6	0	0
T6	2200	0	0	0
T7	3187	6	0	0
T17	3146	0	0	0
T18	15768	1	0	0
T19	2466	0	0	0
T20	9347	0	0	0
T58	0	2	0	0
T86	0	2	0	0
T111	0	1	0	0
T112	0	4	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	447980235	3969	0	0
TransStop_A	447980235	2043	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447980235	3969	0	0
T1	178909	5	0	0
T2	118722	110	0	0
T3	0	81	0	0
T4	64624	0	0	0
T5	3945	6	0	0
T6	2200	0	0	0
T7	3187	10	0	0
T17	3146	0	0	0
T18	15768	1	0	0
T19	2466	0	0	0
T20	9347	0	0	0
T58	0	7	0	0
T86	0	4	0	0
T111	0	1	0	0
T112	0	10	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447980235	2043	0	0
T1	178909	3	0	0
T2	118722	48	0	0
T3	0	37	0	0
T4	64624	0	0	0
T5	3945	5	0	0
T6	2200	0	0	0
T7	3187	7	0	0
T17	3146	0	0	0
T18	15768	1	0	0
T19	2466	0	0	0
T20	9347	0	0	0
T58	0	2	0	0
T86	0	1	0	0
T111	0	1	0	0
T112	0	3	0	0