Unified Coverage Report :: Module :: clkmgr_csr_assert_fpv

Module : clkmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_clkmgr_csr_assert_0/clkmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.clkmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : clkmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	153651632	4807602	0	0
clk_enables_rd_A	153651632	58182	0	0
clk_hints_rd_A	153651632	51851	0	0
extclk_ctrl_rd_A	153651632	66258	0	0
extclk_ctrl_regwen_rd_A	153651632	49204	0	0
jitter_enable_rd_A	153651632	72569	0	0
jitter_regwen_rd_A	153651632	54906	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	4807602	0	0
T2	323953	118094	0	0
T3	0	137250	0	0
T4	26496	0	0	0
T11	0	95038	0	0
T12	0	70750	0	0
T16	0	97222	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	0	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T22	999	0	0	0
T23	2192	0	0	0
T24	115084	0	0	0
T70	0	125840	0	0
T71	0	40661	0	0
T72	0	55351	0	0
T73	0	61871	0	0
T74	0	71522	0	0

clk_enables_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	58182	0	0
T15	602361	8	0	0
T16	286828	0	0	0
T27	604272	0	0	0
T70	0	5414	0	0
T71	0	1581	0	0
T72	0	2263	0	0
T132	2524	1	0	0
T133	2336	6	0	0
T134	0	2	0	0
T135	0	4	0	0
T136	0	1982	0	0
T137	0	1	0	0
T138	2278	0	0	0
T139	22026	0	0	0
T140	2030	0	0	0
T141	1661	0	0	0
T142	1105	0	0	0

clk_hints_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	51851	0	0
T15	602361	6	0	0
T16	286828	0	0	0
T27	604272	0	0	0
T70	0	4973	0	0
T71	0	1516	0	0
T72	0	2047	0	0
T132	2524	0	0	0
T133	2336	4	0	0
T134	0	4	0	0
T135	0	13	0	0
T136	0	1635	0	0
T137	0	7	0	0
T138	2278	0	0	0
T139	22026	0	0	0
T140	2030	0	0	0
T141	1661	0	0	0
T142	1105	0	0	0
T143	0	5	0	0

extclk_ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	66258	0	0
T1	171746	0	0	0
T2	323953	0	0	0
T4	26496	0	0	0
T6	814	5	0	0
T7	2581	0	0	0
T15	0	2	0	0
T17	1572	0	0	0
T18	1419	0	0	0
T19	2367	45	0	0
T20	1963	0	0	0
T21	1339	0	0	0
T24	0	115	0	0
T28	0	58	0	0
T29	0	95	0	0
T77	0	73	0	0
T87	0	19	0	0
T144	0	18	0	0
T145	0	24	0	0

extclk_ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	49204	0	0
T3	284597	0	0	0
T24	115084	65	0	0
T28	25268	40	0	0
T29	32801	41	0	0
T30	97943	0	0	0
T32	966	0	0	0
T40	7543	0	0	0
T70	0	4250	0	0
T71	0	1440	0	0
T72	0	1811	0	0
T77	0	53	0	0
T85	1257	0	0	0
T86	2615	0	0	0
T87	1813	0	0	0
T136	0	1559	0	0
T146	0	38	0	0
T147	0	35	0	0

jitter_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	72569	0	0
T15	602361	293	0	0
T16	286828	0	0	0
T27	604272	0	0	0
T70	0	5801	0	0
T71	0	1917	0	0
T72	0	2733	0	0
T132	2524	114	0	0
T133	2336	125	0	0
T134	0	82	0	0
T135	0	255	0	0
T136	0	1918	0	0
T138	2278	0	0	0
T139	22026	0	0	0
T140	2030	0	0	0
T141	1661	0	0	0
T142	1105	0	0	0
T148	0	95	0	0

jitter_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153651632	54906	0	0
T70	443398	4959	0	0
T71	0	1519	0	0
T72	0	2064	0	0
T93	0	1506	0	0
T113	43919	0	0	0
T134	1807	0	0	0
T136	0	1596	0	0
T149	0	1951	0	0
T150	0	935	0	0
T151	0	4453	0	0
T152	0	789	0	0
T153	0	1413	0	0
T154	2300	0	0	0
T155	885	0	0	0
T156	1343	0	0	0
T157	2843	0	0	0
T158	2295	0	0	0
T159	42865	0	0	0
T160	2037	0	0	0