Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : clkmgr_div_sva_if
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.clkmgr_div2_sva_if 100.00 100.00 100.00 100.00
tb.dut.clkmgr_div4_sva_if 100.00 100.00 100.00 100.00



Module Instance : tb.dut.clkmgr_div2_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.clkmgr_div4_sva_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.65 100.00 93.24 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : clkmgr_div_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Module : clkmgr_div_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT1,T2,T17
11CoveredT6,T1,T2

Assert Coverage for Module : clkmgr_div_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 419408116 4510 0 0
g_div2.Div2Whole_A 419408116 5284 0 0
g_div4.Div4Stepped_A 208936216 4420 0 0
g_div4.Div4Whole_A 208936216 5040 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 419408116 4510 0 0
T1 171747 12 0 0
T2 112372 128 0 0
T3 0 79 0 0
T4 62038 0 0 0
T6 2112 2 0 0
T7 3060 0 0 0
T17 3020 3 0 0
T18 15137 0 0 0
T19 2368 6 0 0
T20 8973 16 0 0
T21 5146 3 0 0
T23 0 11 0 0
T87 0 8 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 419408116 5284 0 0
T1 171747 19 0 0
T2 112372 132 0 0
T4 62038 0 0 0
T6 2112 2 0 0
T7 3060 0 0 0
T17 3020 7 0 0
T18 15137 0 0 0
T19 2368 11 0 0
T20 8973 19 0 0
T21 5146 7 0 0
T23 0 12 0 0
T85 0 3 0 0
T87 0 8 0 0

g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936216 4420 0 0
T1 85908 11 0 0
T2 561675 125 0 0
T3 0 79 0 0
T4 16835 0 0 0
T6 1080 2 0 0
T7 1518 0 0 0
T17 1567 3 0 0
T18 7550 0 0 0
T19 1303 6 0 0
T20 5208 16 0 0
T21 2770 2 0 0
T23 0 11 0 0
T87 0 8 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936216 5040 0 0
T1 85908 14 0 0
T2 561675 132 0 0
T4 16835 0 0 0
T6 1080 2 0 0
T7 1518 0 0 0
T17 1567 6 0 0
T18 7550 0 0 0
T19 1303 11 0 0
T20 5208 14 0 0
T21 2770 7 0 0
T23 0 12 0 0
T85 0 3 0 0
T87 0 8 0 0

Line Coverage for Instance : tb.dut.clkmgr_div2_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT1,T2,T17
11CoveredT6,T1,T2

Assert Coverage for Instance : tb.dut.clkmgr_div2_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div2.Div2Stepped_A 419408116 4510 0 0
g_div2.Div2Whole_A 419408116 5284 0 0


g_div2.Div2Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 419408116 4510 0 0
T1 171747 12 0 0
T2 112372 128 0 0
T3 0 79 0 0
T4 62038 0 0 0
T6 2112 2 0 0
T7 3060 0 0 0
T17 3020 3 0 0
T18 15137 0 0 0
T19 2368 6 0 0
T20 8973 16 0 0
T21 5146 3 0 0
T23 0 11 0 0
T87 0 8 0 0

g_div2.Div2Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 419408116 5284 0 0
T1 171747 19 0 0
T2 112372 132 0 0
T4 62038 0 0 0
T6 2112 2 0 0
T7 3060 0 0 0
T17 3020 7 0 0
T18 15137 0 0 0
T19 2368 11 0 0
T20 8973 19 0 0
T21 5146 7 0 0
T23 0 12 0 0
T85 0 3 0 0
T87 0 8 0 0

Line Coverage for Instance : tb.dut.clkmgr_div4_sva_if
Line No.TotalCoveredPercent
TOTAL22100.00
ALWAYS2511100.00
ALWAYS2811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_div_sva_if.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
25 1 1
28 1 1


Cond Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       25
 EXPRESSION (div_step_down_req_i && ((!scanmode)))
             ---------1---------    ------2------
-1--2-StatusTests
01CoveredT5,T6,T7
10CoveredT1,T2,T17
11CoveredT6,T1,T2

Assert Coverage for Instance : tb.dut.clkmgr_div4_sva_if
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
g_div4.Div4Stepped_A 208936216 4420 0 0
g_div4.Div4Whole_A 208936216 5040 0 0


g_div4.Div4Stepped_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936216 4420 0 0
T1 85908 11 0 0
T2 561675 125 0 0
T3 0 79 0 0
T4 16835 0 0 0
T6 1080 2 0 0
T7 1518 0 0 0
T17 1567 3 0 0
T18 7550 0 0 0
T19 1303 6 0 0
T20 5208 16 0 0
T21 2770 2 0 0
T23 0 11 0 0
T87 0 8 0 0

g_div4.Div4Whole_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 208936216 5040 0 0
T1 85908 14 0 0
T2 561675 132 0 0
T4 16835 0 0 0
T6 1080 2 0 0
T7 1518 0 0 0
T17 1567 6 0 0
T18 7550 0 0 0
T19 1303 11 0 0
T20 5208 14 0 0
T21 2770 7 0 0
T23 0 12 0 0
T85 0 3 0 0
T87 0 8 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%