Unified Coverage Report :: Module :: clkmgr_pwrmgr_sva_if

Module : clkmgr_pwrmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_pwrmgr_sva_if_0.1/clkmgr_pwrmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_pwrmgr_main_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_io_sva_if	100.00						100.00
tb.dut.clkmgr_pwrmgr_usb_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_pwrmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	458112681	408	0	0
StatusRise_A	458112681	408	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458112681	408	0	0
T3	853791	0	0	0
T22	2997	4	0	0
T23	6576	0	0	0
T24	345252	0	0	0
T28	75804	0	0	0
T29	98403	0	0	0
T32	2898	0	0	0
T38	0	12	0	0
T39	0	11	0	0
T85	3771	0	0	0
T86	7845	0	0	0
T87	5439	0	0	0
T161	0	6	0	0
T162	0	20	0	0
T163	0	3	0	0
T164	0	15	0	0
T165	0	4	0	0
T166	0	11	0	0
T167	0	8	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	458112681	408	0	0
T3	853791	0	0	0
T22	2997	4	0	0
T23	6576	0	0	0
T24	345252	0	0	0
T28	75804	0	0	0
T29	98403	0	0	0
T32	2898	0	0	0
T38	0	12	0	0
T39	0	11	0	0
T85	3771	0	0	0
T86	7845	0	0	0
T87	5439	0	0	0
T161	0	6	0	0
T162	0	20	0	0
T163	0	3	0	0
T164	0	15	0	0
T165	0	4	0	0
T166	0	11	0	0
T167	0	8	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_main_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	152704227	135	0	0
StatusRise_A	152704227	135	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	135	0	0
T3	284597	0	0	0
T22	999	1	0	0
T23	2192	0	0	0
T24	115084	0	0	0
T28	25268	0	0	0
T29	32801	0	0	0
T32	966	0	0	0
T38	0	5	0	0
T39	0	5	0	0
T85	1257	0	0	0
T86	2615	0	0	0
T87	1813	0	0	0
T161	0	3	0	0
T162	0	8	0	0
T163	0	1	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	135	0	0
T3	284597	0	0	0
T22	999	1	0	0
T23	2192	0	0	0
T24	115084	0	0	0
T28	25268	0	0	0
T29	32801	0	0	0
T32	966	0	0	0
T38	0	5	0	0
T39	0	5	0	0
T85	1257	0	0	0
T86	2615	0	0	0
T87	1813	0	0	0
T161	0	3	0	0
T162	0	8	0	0
T163	0	1	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_io_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	152704227	137	0	0
StatusRise_A	152704227	137	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	137	0	0
T3	284597	0	0	0
T22	999	1	0	0
T23	2192	0	0	0
T24	115084	0	0	0
T28	25268	0	0	0
T29	32801	0	0	0
T32	966	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T85	1257	0	0	0
T86	2615	0	0	0
T87	1813	0	0	0
T161	0	2	0	0
T162	0	7	0	0
T163	0	1	0	0
T164	0	7	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	2	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	137	0	0
T3	284597	0	0	0
T22	999	1	0	0
T23	2192	0	0	0
T24	115084	0	0	0
T28	25268	0	0	0
T29	32801	0	0	0
T32	966	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T85	1257	0	0	0
T86	2615	0	0	0
T87	1813	0	0	0
T161	0	2	0	0
T162	0	7	0	0
T163	0	1	0	0
T164	0	7	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_pwrmgr_usb_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
StatusFall_A	152704227	136	0	0
StatusRise_A	152704227	136	0	0

StatusFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	136	0	0
T3	284597	0	0	0
T22	999	2	0	0
T23	2192	0	0	0
T24	115084	0	0	0
T28	25268	0	0	0
T29	32801	0	0	0
T32	966	0	0	0
T38	0	3	0	0
T39	0	3	0	0
T85	1257	0	0	0
T86	2615	0	0	0
T87	1813	0	0	0
T161	0	1	0	0
T162	0	5	0	0
T163	0	1	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	5	0	0
T167	0	3	0	0

StatusRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	152704227	136	0	0
T3	284597	0	0	0
T22	999	2	0	0
T23	2192	0	0	0
T24	115084	0	0	0
T28	25268	0	0	0
T29	32801	0	0	0
T32	966	0	0	0
T38	0	3	0	0
T39	0	3	0	0
T85	1257	0	0	0
T86	2615	0	0	0
T87	1813	0	0	0
T161	0	1	0	0
T162	0	5	0	0
T163	0	1	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	5	0	0
T167	0	3	0	0