Unified Coverage Report :: Module :: clkmgr_cg_en_sva_if

Module : clkmgr_cg_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_cg_io_div2_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_timers	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_secure	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_infra	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div4_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_div2_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_io_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_usb_peri	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_aes	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_hmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_kmac	100.00	100.00	100.00				100.00
tb.dut.clkmgr_cg_main_otbn	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_cg_io_div2_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_timers

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_secure

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_infra

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div4_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_div2_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_io_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_usb_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_aes

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_hmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_kmac

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_cg_main_otbn

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_cg_en_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Module : clkmgr_cg_en_sva_if

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Module : clkmgr_cg_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	2147483647	47687	0	0
CgEnOn_A	2147483647	38469	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	47687	0	0
T1	658421	43	0	0
T2	2708882	509	0	0
T3	202013	77	0	0
T4	320658	30	0	0
T5	14476	14	0	0
T6	8129	3	0	0
T7	11709	12	0	0
T17	18590	3	0	0
T18	92008	6	0	0
T19	14870	3	0	0
T20	57456	3	0	0
T21	12070	0	0	0
T22	7330	6	0	0
T23	14740	0	0	0
T24	315107	0	0	0
T28	157932	0	0	0
T29	121484	0	0	0
T32	1971	0	0	0
T38	0	25	0	0
T39	0	15	0	0
T71	0	5	0	0
T85	1612	0	0	0
T86	2725	7	0	0
T87	3698	0	0	0
T161	0	10	0	0
T162	0	35	0	0
T163	0	5	0	0
T164	0	35	0	0
T165	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	38469	0	0
T1	479513	28	0	0
T2	2477788	480	0	0
T3	191403	482	0	0
T4	193998	0	0	0
T5	3944	11	0	0
T6	2199	0	0	0
T7	3186	9	0	0
T11	0	221	0	0
T12	0	12	0	0
T17	12425	0	0	0
T18	61103	3	0	0
T19	10037	0	0	0
T20	39137	0	0	0
T21	16224	0	0	0
T22	8862	9	0	0
T23	18146	0	0	0
T24	195224	0	0	0
T28	151609	0	0	0
T29	116620	0	0	0
T32	1892	0	0	0
T38	0	37	0	0
T39	0	24	0	0
T55	0	13	0	0
T71	0	4	0	0
T85	1547	0	0	0
T86	2615	0	0	0
T87	3551	0	0	0
T111	0	2	0	0
T161	0	16	0	0
T162	0	35	0	0
T163	0	5	0	0
T164	0	35	0	0
T165	0	5	0	0
T166	0	4	0	0
T167	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	208935804	144	0	0
CgEnOn_A	208935804	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208935804	144	0	0
T2	561675	1	0	0
T4	16835	0	0	0
T17	1566	0	0	0
T18	7549	0	0	0
T19	1302	0	0	0
T20	5207	0	0	0
T21	2769	0	0	0
T22	1088	1	0	0
T23	2390	0	0	0
T24	32056	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T71	0	1	0	0
T161	0	2	0	0
T162	0	7	0	0
T163	0	1	0	0
T164	0	7	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208935804	144	0	0
T2	561675	1	0	0
T4	16835	0	0	0
T17	1566	0	0	0
T18	7549	0	0	0
T19	1302	0	0	0
T20	5207	0	0	0
T21	2769	0	0	0
T22	1088	1	0	0
T23	2390	0	0	0
T24	32056	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T71	0	1	0	0
T161	0	2	0	0
T162	0	7	0	0
T163	0	1	0	0
T164	0	7	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104467283	144	0	0
CgEnOn_A	104467283	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104467283	144	0	0
T2	280836	1	0	0
T4	8417	0	0	0
T17	782	0	0	0
T18	3775	0	0	0
T19	650	0	0	0
T20	2601	0	0	0
T21	1385	0	0	0
T22	544	1	0	0
T23	1194	0	0	0
T24	16028	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T71	0	1	0	0
T161	0	2	0	0
T162	0	7	0	0
T163	0	1	0	0
T164	0	7	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104467283	144	0	0
T2	280836	1	0	0
T4	8417	0	0	0
T17	782	0	0	0
T18	3775	0	0	0
T19	650	0	0	0
T20	2601	0	0	0
T21	1385	0	0	0
T22	544	1	0	0
T23	1194	0	0	0
T24	16028	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T71	0	1	0	0
T161	0	2	0	0
T162	0	7	0	0
T163	0	1	0	0
T164	0	7	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104467283	144	0	0
CgEnOn_A	104467283	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104467283	144	0	0
T2	280836	1	0	0
T4	8417	0	0	0
T17	782	0	0	0
T18	3775	0	0	0
T19	650	0	0	0
T20	2601	0	0	0
T21	1385	0	0	0
T22	544	1	0	0
T23	1194	0	0	0
T24	16028	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T71	0	1	0	0
T161	0	2	0	0
T162	0	7	0	0
T163	0	1	0	0
T164	0	7	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104467283	144	0	0
T2	280836	1	0	0
T4	8417	0	0	0
T17	782	0	0	0
T18	3775	0	0	0
T19	650	0	0	0
T20	2601	0	0	0
T21	1385	0	0	0
T22	544	1	0	0
T23	1194	0	0	0
T24	16028	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T71	0	1	0	0
T161	0	2	0	0
T162	0	7	0	0
T163	0	1	0	0
T164	0	7	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_timers

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104467283	144	0	0
CgEnOn_A	104467283	144	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104467283	144	0	0
T2	280836	1	0	0
T4	8417	0	0	0
T17	782	0	0	0
T18	3775	0	0	0
T19	650	0	0	0
T20	2601	0	0	0
T21	1385	0	0	0
T22	544	1	0	0
T23	1194	0	0	0
T24	16028	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T71	0	1	0	0
T161	0	2	0	0
T162	0	7	0	0
T163	0	1	0	0
T164	0	7	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104467283	144	0	0
T2	280836	1	0	0
T4	8417	0	0	0
T17	782	0	0	0
T18	3775	0	0	0
T19	650	0	0	0
T20	2601	0	0	0
T21	1385	0	0	0
T22	544	1	0	0
T23	1194	0	0	0
T24	16028	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T71	0	1	0	0
T161	0	2	0	0
T162	0	7	0	0
T163	0	1	0	0
T164	0	7	0	0
T165	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	419407684	144	0	0
CgEnOn_A	419407684	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419407684	144	0	0
T2	112372	1	0	0
T4	62037	0	0	0
T17	3019	0	0	0
T18	15137	0	0	0
T19	2367	0	0	0
T20	8973	0	0	0
T21	5146	0	0	0
T22	2255	1	0	0
T23	4295	0	0	0
T24	115084	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T71	0	1	0	0
T161	0	2	0	0
T162	0	7	0	0
T163	0	1	0	0
T164	0	7	0	0
T165	0	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419407684	137	0	0
T3	191403	0	0	0
T22	2255	1	0	0
T23	4295	0	0	0
T24	115084	0	0	0
T28	151609	0	0	0
T29	116620	0	0	0
T32	1892	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T85	1547	0	0	0
T86	2615	0	0	0
T87	3551	0	0	0
T161	0	2	0	0
T162	0	7	0	0
T163	0	1	0	0
T164	0	7	0	0
T165	0	1	0	0
T166	0	4	0	0
T167	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	447979787	136	0	0
CgEnOn_A	447979787	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447979787	136	0	0
T3	202013	0	0	0
T22	2355	1	0	0
T23	4473	0	0	0
T24	119883	0	0	0
T28	157932	0	0	0
T29	121484	0	0	0
T32	1971	0	0	0
T38	0	5	0	0
T39	0	5	0	0
T70	0	1	0	0
T85	1612	0	0	0
T86	2725	0	0	0
T87	3698	0	0	0
T161	0	3	0	0
T162	0	8	0	0
T163	0	1	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447979787	135	0	0
T3	202013	0	0	0
T22	2355	1	0	0
T23	4473	0	0	0
T24	119883	0	0	0
T28	157932	0	0	0
T29	121484	0	0	0
T32	1971	0	0	0
T38	0	5	0	0
T39	0	5	0	0
T85	1612	0	0	0
T86	2725	0	0	0
T87	3698	0	0	0
T161	0	3	0	0
T162	0	8	0	0
T163	0	1	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_secure

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	447979787	136	0	0
CgEnOn_A	447979787	135	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447979787	136	0	0
T3	202013	0	0	0
T22	2355	1	0	0
T23	4473	0	0	0
T24	119883	0	0	0
T28	157932	0	0	0
T29	121484	0	0	0
T32	1971	0	0	0
T38	0	5	0	0
T39	0	5	0	0
T70	0	1	0	0
T85	1612	0	0	0
T86	2725	0	0	0
T87	3698	0	0	0
T161	0	3	0	0
T162	0	8	0	0
T163	0	1	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447979787	135	0	0
T3	202013	0	0	0
T22	2355	1	0	0
T23	4473	0	0	0
T24	119883	0	0	0
T28	157932	0	0	0
T29	121484	0	0	0
T32	1971	0	0	0
T38	0	5	0	0
T39	0	5	0	0
T85	1612	0	0	0
T86	2725	0	0	0
T87	3698	0	0	0
T161	0	3	0	0
T162	0	8	0	0
T163	0	1	0	0
T164	0	4	0	0
T165	0	2	0	0
T166	0	2	0	0
T167	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_infra

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	214833881	137	0	0
CgEnOn_A	214833881	137	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214833881	137	0	0
T3	968297	0	0	0
T22	1112	2	0	0
T23	2147	0	0	0
T24	57544	0	0	0
T28	75808	0	0	0
T29	58312	0	0	0
T32	945	0	0	0
T38	0	3	0	0
T39	0	3	0	0
T85	774	0	0	0
T86	1308	0	0	0
T87	1775	0	0	0
T161	0	1	0	0
T162	0	5	0	0
T163	0	1	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	5	0	0
T167	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214833881	137	0	0
T3	968297	0	0	0
T22	1112	2	0	0
T23	2147	0	0	0
T24	57544	0	0	0
T28	75808	0	0	0
T29	58312	0	0	0
T32	945	0	0	0
T38	0	3	0	0
T39	0	3	0	0
T85	774	0	0	0
T86	1308	0	0	0
T87	1775	0	0	0
T161	0	1	0	0
T162	0	5	0	0
T163	0	1	0	0
T164	0	4	0	0
T165	0	1	0	0
T166	0	5	0	0
T167	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T38,T39
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div4_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	104467283	7488	0	0
CgEnOn_A	104467283	5190	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104467283	7488	0	0
T1	42951	12	0	0
T2	280836	134	0	0
T4	8417	10	0	0
T5	934	1	0	0
T6	540	1	0	0
T7	759	1	0	0
T17	782	1	0	0
T18	3775	1	0	0
T19	650	1	0	0
T20	2601	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	104467283	5190	0	0
T1	42951	7	0	0
T2	280836	125	0	0
T3	0	133	0	0
T4	8417	0	0	0
T11	0	74	0	0
T12	0	12	0	0
T17	782	0	0	0
T18	3775	0	0	0
T19	650	0	0	0
T20	2601	0	0	0
T21	1385	0	0	0
T22	544	1	0	0
T23	1194	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T55	0	3	0	0
T161	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T38,T39
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_div2_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	208935804	7492	0	0
CgEnOn_A	208935804	5194	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208935804	7492	0	0
T1	85908	14	0	0
T2	561675	128	0	0
T4	16835	10	0	0
T5	1867	1	0	0
T6	1080	1	0	0
T7	1518	1	0	0
T17	1566	1	0	0
T18	7549	1	0	0
T19	1302	1	0	0
T20	5207	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208935804	5194	0	0
T1	85908	9	0	0
T2	561675	119	0	0
T3	0	135	0	0
T4	16835	0	0	0
T11	0	72	0	0
T17	1566	0	0	0
T18	7549	0	0	0
T19	1302	0	0	0
T20	5207	0	0	0
T21	2769	0	0	0
T22	1088	1	0	0
T23	2390	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T55	0	6	0	0
T111	0	1	0	0
T161	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T38,T39
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_io_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	419407684	7538	0	0
CgEnOn_A	419407684	5233	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419407684	7538	0	0
T1	171746	13	0	0
T2	112372	126	0	0
T4	62037	10	0	0
T5	3787	1	0	0
T6	2111	1	0	0
T7	3060	1	0	0
T17	3019	1	0	0
T18	15137	1	0	0
T19	2367	1	0	0
T20	8973	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419407684	5233	0	0
T1	171746	8	0	0
T2	112372	116	0	0
T3	0	137	0	0
T4	62037	0	0	0
T11	0	75	0	0
T17	3019	0	0	0
T18	15137	0	0	0
T19	2367	0	0	0
T20	8973	0	0	0
T21	5146	0	0	0
T22	2255	1	0	0
T23	4295	0	0	0
T38	0	4	0	0
T39	0	3	0	0
T55	0	4	0	0
T111	0	1	0	0
T161	0	2	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T22,T38,T39
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_usb_peri

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	214833881	7519	0	0
CgEnOn_A	214833881	5215	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214833881	7519	0	0
T1	85877	15	0	0
T2	568726	133	0	0
T4	31020	10	0	0
T5	1893	1	0	0
T6	1055	1	0	0
T7	1530	1	0	0
T17	1510	1	0	0
T18	7569	1	0	0
T19	1183	1	0	0
T20	4486	1	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214833881	5215	0	0
T1	85877	10	0	0
T2	568726	123	0	0
T3	0	131	0	0
T4	31020	0	0	0
T11	0	74	0	0
T17	1510	0	0	0
T18	7569	0	0	0
T19	1183	0	0	0
T20	4486	0	0	0
T21	2573	0	0	0
T22	1112	2	0	0
T23	2147	0	0	0
T38	0	3	0	0
T39	0	3	0	0
T55	0	5	0	0
T111	0	1	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T5,T7,T1
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_aes

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	447979787	4242	0	0
CgEnOn_A	447979787	4241	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447979787	4242	0	0
T1	178908	4	0	0
T2	118722	116	0	0
T3	0	77	0	0
T4	64623	0	0	0
T5	3944	11	0	0
T6	2199	0	0	0
T7	3186	9	0	0
T17	3146	0	0	0
T18	15768	3	0	0
T19	2466	0	0	0
T20	9346	0	0	0
T22	0	1	0	0
T38	0	5	0	0
T58	0	8	0	0
T86	0	7	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447979787	4241	0	0
T1	178908	4	0	0
T2	118722	116	0	0
T3	0	77	0	0
T4	64623	0	0	0
T5	3944	11	0	0
T6	2199	0	0	0
T7	3186	9	0	0
T17	3146	0	0	0
T18	15768	3	0	0
T19	2466	0	0	0
T20	9346	0	0	0
T22	0	1	0	0
T38	0	5	0	0
T58	0	8	0	0
T86	0	7	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T5,T7,T1
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_hmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	447979787	4119	0	0
CgEnOn_A	447979787	4118	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447979787	4119	0	0
T1	178908	6	0	0
T2	118722	132	0	0
T3	0	83	0	0
T4	64623	0	0	0
T5	3944	12	0	0
T6	2199	0	0	0
T7	3186	12	0	0
T17	3146	0	0	0
T18	15768	3	0	0
T19	2466	0	0	0
T20	9346	0	0	0
T22	0	1	0	0
T38	0	5	0	0
T58	0	5	0	0
T86	0	3	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447979787	4118	0	0
T1	178908	6	0	0
T2	118722	132	0	0
T3	0	83	0	0
T4	64623	0	0	0
T5	3944	12	0	0
T6	2199	0	0	0
T7	3186	12	0	0
T17	3146	0	0	0
T18	15768	3	0	0
T19	2466	0	0	0
T20	9346	0	0	0
T22	0	1	0	0
T38	0	5	0	0
T58	0	5	0	0
T86	0	3	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T5,T7,T1
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_kmac

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	447979787	4055	0	0
CgEnOn_A	447979787	4054	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447979787	4055	0	0
T1	178908	5	0	0
T2	118722	115	0	0
T3	0	72	0	0
T4	64623	0	0	0
T5	3944	8	0	0
T6	2199	0	0	0
T7	3186	12	0	0
T17	3146	0	0	0
T18	15768	3	0	0
T19	2466	0	0	0
T20	9346	0	0	0
T22	0	1	0	0
T38	0	5	0	0
T58	0	5	0	0
T86	0	5	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447979787	4054	0	0
T1	178908	5	0	0
T2	118722	115	0	0
T3	0	72	0	0
T4	64623	0	0	0
T5	3944	8	0	0
T6	2199	0	0	0
T7	3186	12	0	0
T17	3146	0	0	0
T18	15768	3	0	0
T19	2466	0	0	0
T20	9346	0	0	0
T22	0	1	0	0
T38	0	5	0	0
T58	0	5	0	0
T86	0	5	0	0

Line Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	24	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_cg_en_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (ip_clk_en && sw_clk_en)
             ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T5,T7,T1
1	1	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.clkmgr_cg_main_otbn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CgEnOff_A	447979787	4105	0	0
CgEnOn_A	447979787	4104	0	0

CgEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447979787	4105	0	0
T1	178908	5	0	0
T2	118722	110	0	0
T3	0	81	0	0
T4	64623	0	0	0
T5	3944	6	0	0
T6	2199	0	0	0
T7	3186	10	0	0
T17	3146	0	0	0
T18	15768	1	0	0
T19	2466	0	0	0
T20	9346	0	0	0
T22	0	1	0	0
T38	0	5	0	0
T58	0	7	0	0
T86	0	4	0	0

CgEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	447979787	4104	0	0
T1	178908	5	0	0
T2	118722	110	0	0
T3	0	81	0	0
T4	64623	0	0	0
T5	3944	6	0	0
T6	2199	0	0	0
T7	3186	10	0	0
T17	3146	0	0	0
T18	15768	1	0	0
T19	2466	0	0	0
T20	9346	0	0	0
T22	0	1	0	0
T38	0	5	0	0
T58	0	7	0	0
T86	0	4	0	0