Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_clkmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	652529	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3902650

1

T1

1424

T6

45

T5

192

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1115749	1			T1	395		T6	76		T5	18
values[0x0]	1581767	1			T1	1296		T6	27		T5	166
values[0x1]	1857663	1			T1	1293		T6	30		T5	213

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	354498	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4200681

1

T1

1843

T6

58

T5

253

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	17984	1			T1	15		T2	709		T10	633
valid_sources[0x01]	18658	1			T1	14		T6	1		T2	733
valid_sources[0x02]	18777	1			T1	4		T2	800		T10	724
valid_sources[0x03]	19943	1			T1	5		T6	3		T2	671
valid_sources[0x04]	18382	1			T1	5		T2	768		T10	624
valid_sources[0x05]	16654	1			T1	18		T6	1		T2	748
valid_sources[0x06]	17648	1			T1	17		T18	2		T2	702
valid_sources[0x07]	16809	1			T1	12		T6	8		T2	729
valid_sources[0x08]	18171	1			T1	8		T6	1		T18	1
valid_sources[0x09]	18110	1			T1	13		T2	648		T3	3
valid_sources[0x0a]	17240	1			T1	13		T2	736		T10	738
valid_sources[0x0b]	17390	1			T1	8		T2	817		T3	5
valid_sources[0x0c]	17523	1			T1	13		T2	645		T3	2
valid_sources[0x0d]	17629	1			T1	10		T18	1		T2	790
valid_sources[0x0e]	19143	1			T1	19		T18	2		T2	781
valid_sources[0x0f]	18281	1			T1	8		T17	5		T2	783
valid_sources[0x10]	17569	1			T1	17		T2	728		T10	685
valid_sources[0x11]	17328	1			T1	13		T6	1		T2	706
valid_sources[0x12]	15980	1			T1	15		T6	1		T2	709
valid_sources[0x13]	15993	1			T1	13		T2	735		T10	613
valid_sources[0x14]	17105	1			T1	17		T2	678		T10	673
valid_sources[0x15]	17677	1			T1	11		T6	1		T2	736
valid_sources[0x16]	18631	1			T1	10		T6	2		T2	721
valid_sources[0x17]	16820	1			T1	12		T2	804		T3	9
valid_sources[0x18]	17729	1			T1	13		T18	1		T2	731
valid_sources[0x19]	17496	1			T1	16		T2	718		T10	708
valid_sources[0x1a]	20357	1			T1	14		T2	734		T3	1
valid_sources[0x1b]	17661	1			T1	7		T18	2		T2	662
valid_sources[0x1c]	15174	1			T1	11		T18	1		T2	736
valid_sources[0x1d]	18121	1			T1	12		T17	3		T2	747
valid_sources[0x1e]	19429	1			T1	18		T18	1		T2	676
valid_sources[0x1f]	18091	1			T1	9		T6	1		T2	751
valid_sources[0x20]	16479	1			T1	12		T2	778		T3	11
valid_sources[0x21]	18639	1			T1	11		T6	1		T2	737
valid_sources[0x22]	17957	1			T1	15		T6	1		T18	2
valid_sources[0x23]	17023	1			T1	20		T2	776		T19	19
valid_sources[0x24]	17864	1			T1	14		T6	1		T2	740
valid_sources[0x25]	18066	1			T1	11		T18	1		T2	741
valid_sources[0x26]	17624	1			T1	15		T6	1		T2	702
valid_sources[0x27]	18259	1			T1	15		T6	3		T18	1
valid_sources[0x28]	17204	1			T1	6		T6	2		T2	734
valid_sources[0x29]	18800	1			T1	8		T2	778		T10	669
valid_sources[0x2a]	16411	1			T1	15		T2	751		T10	616
valid_sources[0x2b]	16793	1			T1	8		T2	716		T10	676
valid_sources[0x2c]	17090	1			T1	12		T2	771		T3	4
valid_sources[0x2d]	16259	1			T1	10		T2	807		T19	9
valid_sources[0x2e]	16787	1			T1	12		T6	1		T2	727
valid_sources[0x2f]	19661	1			T1	15		T18	2		T2	746
valid_sources[0x30]	15926	1			T1	12		T6	3		T2	806
valid_sources[0x31]	19427	1			T1	7		T6	2		T17	1
valid_sources[0x32]	19461	1			T1	12		T2	717		T3	2
valid_sources[0x33]	17380	1			T1	6		T2	843		T3	7
valid_sources[0x34]	17589	1			T1	11		T6	3		T18	4
valid_sources[0x35]	17778	1			T1	9		T18	3		T2	689
valid_sources[0x36]	17493	1			T1	13		T2	780		T3	2
valid_sources[0x37]	17134	1			T1	18		T2	700		T3	7
valid_sources[0x38]	17681	1			T1	13		T2	743		T10	621
valid_sources[0x39]	16174	1			T1	8		T2	791		T10	578
valid_sources[0x3a]	19212	1			T1	12		T2	699		T3	2
valid_sources[0x3b]	17372	1			T1	11		T2	697		T3	5
valid_sources[0x3c]	17349	1			T1	13		T2	754		T10	618
valid_sources[0x3d]	16917	1			T1	14		T2	729		T3	3
valid_sources[0x3e]	17471	1			T1	11		T6	2		T18	1
valid_sources[0x3f]	18012	1			T1	8		T6	2		T2	731
valid_sources[0x40]	15856	1			T1	15		T2	739		T10	656
valid_sources[0x41]	18044	1			T1	13		T18	1		T2	648
valid_sources[0x42]	16918	1			T1	13		T2	742		T3	2
valid_sources[0x43]	18730	1			T1	11		T6	1		T2	768
valid_sources[0x44]	18618	1			T1	13		T2	651		T3	2
valid_sources[0x45]	17259	1			T1	14		T2	748		T10	670
valid_sources[0x46]	17456	1			T1	12		T6	1		T2	678
valid_sources[0x47]	17101	1			T1	14		T2	708		T3	6
valid_sources[0x48]	17046	1			T1	12		T2	750		T10	678
valid_sources[0x49]	19702	1			T1	13		T6	1		T17	1
valid_sources[0x4a]	17955	1			T1	10		T18	1		T2	779
valid_sources[0x4b]	18795	1			T1	12		T6	1		T2	740
valid_sources[0x4c]	18727	1			T1	10		T18	1		T2	747
valid_sources[0x4d]	18522	1			T1	7		T6	1		T18	2
valid_sources[0x4e]	17234	1			T1	12		T2	746		T3	6
valid_sources[0x4f]	18381	1			T1	13		T6	1		T2	718
valid_sources[0x50]	18167	1			T1	10		T18	1		T2	725
valid_sources[0x51]	18186	1			T1	21		T18	1		T2	677
valid_sources[0x52]	16242	1			T1	9		T6	1		T18	1
valid_sources[0x53]	17116	1			T1	4		T2	710		T3	9
valid_sources[0x54]	18133	1			T1	13		T18	4		T2	799
valid_sources[0x55]	16553	1			T1	13		T17	1		T2	765
valid_sources[0x56]	17394	1			T1	13		T18	2		T2	694
valid_sources[0x57]	17440	1			T1	14		T18	1		T2	749
valid_sources[0x58]	17732	1			T1	12		T18	1		T2	744
valid_sources[0x59]	16716	1			T1	9		T6	2		T2	727
valid_sources[0x5a]	17365	1			T1	13		T2	631		T34	1
valid_sources[0x5b]	18879	1			T1	8		T2	765		T3	1
valid_sources[0x5c]	16549	1			T1	11		T2	717		T19	7
valid_sources[0x5d]	17089	1			T1	11		T2	757		T10	705
valid_sources[0x5e]	15931	1			T1	9		T6	1		T2	764
valid_sources[0x5f]	17030	1			T1	8		T2	719		T3	3
valid_sources[0x60]	16058	1			T1	8		T2	689		T10	603
valid_sources[0x61]	18001	1			T1	6		T2	736		T35	1
valid_sources[0x62]	17733	1			T1	7		T2	749		T34	1
valid_sources[0x63]	17320	1			T1	7		T6	1		T2	709
valid_sources[0x64]	17878	1			T1	9		T6	7		T2	715
valid_sources[0x65]	19164	1			T1	10		T2	717		T3	1
valid_sources[0x66]	17770	1			T1	12		T6	1		T2	824
valid_sources[0x67]	17297	1			T1	14		T6	1		T2	746
valid_sources[0x68]	16375	1			T1	8		T6	1		T2	772
valid_sources[0x69]	16221	1			T1	7		T6	5		T18	1
valid_sources[0x6a]	18122	1			T1	8		T17	4		T2	709
valid_sources[0x6b]	16501	1			T1	10		T2	786		T10	726
valid_sources[0x6c]	18177	1			T1	11		T2	747		T10	633
valid_sources[0x6d]	18446	1			T1	15		T2	685		T10	538
valid_sources[0x6e]	16171	1			T1	10		T2	752		T3	1
valid_sources[0x6f]	19706	1			T1	19		T6	4		T2	666
valid_sources[0x70]	19977	1			T1	21		T2	751		T20	1
valid_sources[0x71]	17421	1			T1	9		T6	1		T2	741
valid_sources[0x72]	16808	1			T1	8		T6	2		T2	722
valid_sources[0x73]	17379	1			T1	8		T2	691		T10	690
valid_sources[0x74]	18715	1			T1	22		T2	754		T3	3
valid_sources[0x75]	18075	1			T1	11		T2	803		T10	503
valid_sources[0x76]	16506	1			T1	7		T2	729		T3	1
valid_sources[0x77]	16405	1			T1	15		T18	1		T2	778
valid_sources[0x78]	16587	1			T1	9		T2	651		T3	1
valid_sources[0x79]	17556	1			T1	4		T18	1		T2	725
valid_sources[0x7a]	18450	1			T1	10		T2	631		T10	673
valid_sources[0x7b]	18809	1			T1	16		T6	1		T2	697
valid_sources[0x7c]	17251	1			T1	9		T2	757		T10	538
valid_sources[0x7d]	17777	1			T1	8		T6	1		T2	704
valid_sources[0x7e]	18223	1			T1	15		T18	2		T2	763
valid_sources[0x7f]	18521	1			T1	14		T2	689		T10	648
valid_sources[0x80]	17603	1			T1	12		T2	731		T3	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

982328

1

T1

195

T6

35

T5

10

values[0x0]

all_enables

biggest_size

1485130

1

T1

792

T6

6

T5

112

values[0x1]

all_enables

biggest_size

1435192

1

T1

437

T6

4

T5

70