Unified Coverage Report :: Module :: clkmgr_gated_clock_sva_if

Module : clkmgr_gated_clock_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_io_div4_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_div2_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_io_peri_sva_if	100.00	100.00	100.00				100.00
tb.dut.clkmgr_usb_peri_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_io_div4_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_div2_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_io_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_usb_peri_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : clkmgr_gated_clock_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T4
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T6,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T4
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T6,T5

---

Assert Coverage for Module : clkmgr_gated_clock_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	1072330020	13309	0	0
GateOpen_A	1072330020	19753	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1072330020	13309	0	0
T1	1507403	100	0	0
T2	2143027	404	0	0
T3	410874	0	0	0
T4	27251	0	0	0
T5	379088	0	0	0
T6	25440	0	0	0
T10	0	151	0	0
T11	0	141	0	0
T13	0	4	0	0
T17	6129	0	0	0
T18	16322	4	0	0
T19	183492	0	0	0
T20	9030	0	0	0
T31	0	9	0	0
T107	0	4	0	0
T109	0	4	0	0
T152	0	4	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1072330020	19753	0	0
T1	1507403	116	0	0
T2	2143027	424	0	0
T3	410874	4	0	0
T4	27251	8	0	0
T5	379088	4	0	0
T6	25440	0	0	0
T10	0	171	0	0
T17	6129	0	0	0
T18	16322	4	0	0
T19	183492	4	0	0
T20	9030	0	0	0
T31	0	13	0	0
T35	0	4	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T4
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T6,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T4
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div4_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	118625965	3184	0	0
GateOpen_A	118625965	4793	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118625965	3184	0	0
T1	263658	24	0	0
T2	394925	97	0	0
T3	45630	0	0	0
T4	1735	0	0	0
T5	39218	0	0	0
T6	2805	0	0	0
T10	0	37	0	0
T11	0	33	0	0
T13	0	1	0	0
T17	670	0	0	0
T18	1791	1	0	0
T19	19090	0	0	0
T20	995	0	0	0
T31	0	2	0	0
T107	0	1	0	0
T109	0	1	0	0
T152	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	118625965	4793	0	0
T1	263658	28	0	0
T2	394925	102	0	0
T3	45630	1	0	0
T4	1735	2	0	0
T5	39218	1	0	0
T6	2805	0	0	0
T10	0	42	0	0
T17	670	0	0	0
T18	1791	1	0	0
T19	19090	1	0	0
T20	995	0	0	0
T31	0	3	0	0
T35	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T4
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T6,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T4
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_div2_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	237252836	3376	0	0
GateOpen_A	237252836	4985	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237252836	3376	0	0
T1	527319	27	0	0
T2	789853	106	0	0
T3	91260	0	0	0
T4	3469	0	0	0
T5	78436	0	0	0
T6	5609	0	0	0
T10	0	38	0	0
T11	0	37	0	0
T13	0	1	0	0
T17	1340	0	0	0
T18	3582	1	0	0
T19	38180	0	0	0
T20	1991	0	0	0
T31	0	2	0	0
T107	0	1	0	0
T109	0	1	0	0
T152	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	237252836	4985	0	0
T1	527319	31	0	0
T2	789853	111	0	0
T3	91260	1	0	0
T4	3469	2	0	0
T5	78436	1	0	0
T6	5609	0	0	0
T10	0	43	0	0
T17	1340	0	0	0
T18	3582	1	0	0
T19	38180	1	0	0
T20	1991	0	0	0
T31	0	3	0	0
T35	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T4
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T6,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T4
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_io_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	473979991	3383	0	0
GateOpen_A	473979991	4996	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473979991	3383	0	0
T1	105479	25	0	0
T2	157923	99	0	0
T3	182653	0	0	0
T4	14698	0	0	0
T5	157007	0	0	0
T6	11350	0	0	0
T10	0	36	0	0
T11	0	35	0	0
T13	0	1	0	0
T17	2746	0	0	0
T18	7299	1	0	0
T19	76466	0	0	0
T20	4029	0	0	0
T31	0	2	0	0
T107	0	1	0	0
T109	0	1	0	0
T152	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	473979991	4996	0	0
T1	105479	29	0	0
T2	157923	104	0	0
T3	182653	1	0	0
T4	14698	2	0	0
T5	157007	1	0	0
T6	11350	0	0	0
T10	0	41	0	0
T17	2746	0	0	0
T18	7299	1	0	0
T19	76466	1	0	0
T20	4029	0	0	0
T31	0	3	0	0
T35	0	1	0	0

Line Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	18	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' or '../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_gated_clock_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
18	1	1

---

Cond Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       18
 EXPRESSION ((sw_clk_en && ip_clk_en) || scanmode)
             ------------1-----------    ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T18,T4
0	1	Covered	T1,T2,T20
1	0	Covered	T1,T6,T5

 LINE       18
 SUB-EXPRESSION (sw_clk_en && ip_clk_en)
                 ----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T18,T4
1	0	Covered	T31,T32,T33
1	1	Covered	T1,T6,T5

---

Assert Coverage for Instance : tb.dut.clkmgr_usb_peri_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
GateClose_A	242471228	3366	0	0
GateOpen_A	242471228	4979	0	0

GateClose_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242471228	3366	0	0
T1	610947	24	0	0
T2	800326	102	0	0
T3	91331	0	0	0
T4	7349	0	0	0
T5	104427	0	0	0
T6	5676	0	0	0
T10	0	40	0	0
T11	0	36	0	0
T13	0	1	0	0
T17	1373	0	0	0
T18	3650	1	0	0
T19	49756	0	0	0
T20	2015	0	0	0
T31	0	3	0	0
T107	0	1	0	0
T109	0	1	0	0
T152	0	1	0	0

GateOpen_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	242471228	4979	0	0
T1	610947	28	0	0
T2	800326	107	0	0
T3	91331	1	0	0
T4	7349	2	0	0
T5	104427	1	0	0
T6	5676	0	0	0
T10	0	45	0	0
T17	1373	0	0	0
T18	3650	1	0	0
T19	49756	1	0	0
T20	2015	0	0	0
T31	0	4	0	0
T35	0	1	0	0