Unified Coverage Report :: Module :: clkmgr_lost_calib_ctrl_en_sva_if

Module : clkmgr_lost_calib_ctrl_en_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_lost_calib_ctrl_en_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if	100.00						100.00
tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_lost_calib_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	829730035	73591	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	829730035	73591	0	0
T1	598225	717	0	0
T2	2521650	1148	0	0
T3	228315	94	0	0
T4	38270	0	0	0
T5	1044220	0	0	0
T6	11820	0	0	0
T10	0	2789	0	0
T11	0	1052	0	0
T12	0	57	0	0
T13	0	52	0	0
T14	0	515	0	0
T15	0	297	0	0
T16	0	95	0	0
T17	6715	0	0	0
T18	8360	0	0	0
T19	438615	0	0	0
T20	10075	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165946007	10884	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	10884	0	0
T1	119645	94	0	0
T2	504330	184	0	0
T3	45663	15	0	0
T4	7654	0	0	0
T5	208844	0	0	0
T6	2364	0	0	0
T10	0	375	0	0
T11	0	156	0	0
T12	0	8	0	0
T13	0	8	0	0
T14	0	69	0	0
T15	0	40	0	0
T16	0	14	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	0	0	0
T20	2015	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_main_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165946007	10709	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	10709	0	0
T1	119645	93	0	0
T2	504330	179	0	0
T3	45663	15	0	0
T4	7654	0	0	0
T5	208844	0	0	0
T6	2364	0	0	0
T10	0	366	0	0
T11	0	132	0	0
T12	0	8	0	0
T13	0	8	0	0
T14	0	67	0	0
T15	0	44	0	0
T16	0	12	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	0	0	0
T20	2015	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_usb_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165946007	14930	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	14930	0	0
T1	119645	144	0	0
T2	504330	229	0	0
T3	45663	19	0	0
T4	7654	0	0	0
T5	208844	0	0	0
T6	2364	0	0	0
T10	0	564	0	0
T11	0	206	0	0
T12	0	13	0	0
T13	0	10	0	0
T14	0	102	0	0
T15	0	59	0	0
T16	0	18	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	0	0	0
T20	2015	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div2_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165946007	14786	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	14786	0	0
T1	119645	145	0	0
T2	504330	232	0	0
T3	45663	19	0	0
T4	7654	0	0	0
T5	208844	0	0	0
T6	2364	0	0	0
T10	0	564	0	0
T11	0	210	0	0
T12	0	11	0	0
T13	0	10	0	0
T14	0	105	0	0
T15	0	56	0	0
T16	0	20	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	0	0	0
T20	2015	0	0	0

Assert Coverage for Instance : tb.dut.clkmgr_lost_calib_io_div4_ctrl_en_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CtrlEnOn_A	165946007	22282	0	0

CtrlEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	22282	0	0
T1	119645	241	0	0
T2	504330	324	0	0
T3	45663	26	0	0
T4	7654	0	0	0
T5	208844	0	0	0
T6	2364	0	0	0
T10	0	920	0	0
T11	0	348	0	0
T12	0	17	0	0
T13	0	16	0	0
T14	0	172	0	0
T15	0	98	0	0
T16	0	31	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	0	0	0
T20	2015	0	0	0