Unified Coverage Report :: Module :: clkmgr_sec_cm_checker_assert

Module : clkmgr_sec_cm_checker_assert

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_sec_cm_checker_assert	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.clkmgr_sec_cm_checker_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : clkmgr_sec_cm_checker_assert

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	23	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' or '../src/lowrisc_dv_clkmgr_sva_0.1/clkmgr_sec_cm_checker_assert.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1

---

Cond Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       23
 EXPRESSION (((!rst_ni)) || disable_sva)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T5
0	1	Unreachable
1	0	Covered	T1,T4,T2

---

Assert Coverage for Module : clkmgr_sec_cm_checker_assert

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AllClkBypReqFalse_A	165946007	163550881	0	0
AllClkBypReqTrue_A	165946007	137773	0	0
IoClkBypReqFalse_A	165946007	163464601	0	2415
IoClkBypReqTrue_A	165946007	219533	0	0
LcClkBypAckFalse_A	165946007	163558013	0	0
LcClkBypAckTrue_A	165946007	130641	0	0

AllClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	163550881	0	0
T1	119645	119470	0	0
T2	504330	503709	0	0
T3	45663	45595	0	0
T4	7654	1069	0	0
T5	208844	208612	0	0
T6	2364	2318	0	0
T17	1343	1243	0	0
T18	1672	1631	0	0
T19	87723	87564	0	0
T20	2015	1894	0	0

AllClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	137773	0	0
T1	119645	465	0	0
T2	504330	1893	0	0
T3	45663	0	0	0
T4	7654	0	0	0
T5	208844	0	0	0
T6	2364	0	0	0
T10	0	1893	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	0	0	0
T20	2015	23	0	0
T34	0	78	0	0
T35	0	317	0	0
T61	0	76	0	0
T68	0	153	0	0
T77	0	51	0	0
T78	0	108	0	0

IoClkBypReqFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	163464601	0	2415
T1	119645	119461	0	3
T2	504330	503571	0	3
T3	45663	45593	0	3
T4	7654	1063	0	3
T5	208844	208610	0	3
T6	2364	2316	0	3
T17	1343	1241	0	3
T18	1672	1629	0	3
T19	87723	87562	0	3
T20	2015	1889	0	3

IoClkBypReqTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	219533	0	0
T1	119645	536	0	0
T2	504330	3249	0	0
T3	45663	0	0	0
T4	7654	0	0	0
T5	208844	0	0	0
T6	2364	0	0	0
T10	0	3219	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	0	0	0
T20	2015	24	0	0
T34	0	110	0	0
T35	0	418	0	0
T61	0	190	0	0
T68	0	250	0	0
T78	0	361	0	0
T80	0	29	0	0

LcClkBypAckFalse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	163558013	0	0
T1	119645	119482	0	0
T2	504330	503695	0	0
T3	45663	45595	0	0
T4	7654	1069	0	0
T5	208844	208612	0	0
T6	2364	2318	0	0
T17	1343	1243	0	0
T18	1672	1631	0	0
T19	87723	87564	0	0
T20	2015	1898	0	0

LcClkBypAckTrue_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	165946007	130641	0	0
T1	119645	345	0	0
T2	504330	2031	0	0
T3	45663	0	0	0
T4	7654	0	0	0
T5	208844	0	0	0
T6	2364	0	0	0
T10	0	2182	0	0
T17	1343	0	0	0
T18	1672	0	0	0
T19	87723	0	0	0
T20	2015	19	0	0
T34	0	64	0	0
T35	0	258	0	0
T61	0	143	0	0
T68	0	150	0	0
T78	0	182	0	0
T106	0	263	0	0