Unified Coverage Report :: Module :: clkmgr_trans_sva_if

Module : clkmgr_trans_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_sva_ifs_0.1/clkmgr_trans_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.clkmgr_aes_trans_sva_if	100.00						100.00
tb.dut.clkmgr_hmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_kmac_trans_sva_if	100.00						100.00
tb.dut.clkmgr_otbn_trans_sva_if	100.00						100.00

---

Module Instance : tb.dut.clkmgr_aes_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_hmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_kmac_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.clkmgr_otbn_trans_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.65	100.00	93.24	100.00		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Assert Coverage for Module : clkmgr_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	2019195172	16407	0	0
TransStop_A	2019195172	8520	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2019195172	16407	0	0
T1	497112	50	0	0
T2	667392	423	0	0
T3	761076	0	0	0
T4	61240	0	0	0
T5	846216	0	0	0
T6	47296	37	0	0
T10	0	226	0	0
T11	0	210	0	0
T13	0	38	0	0
T17	11440	5	0	0
T18	30412	4	0	0
T19	390620	0	0	0
T20	16788	0	0	0
T79	0	3	0	0
T107	0	4	0	0
T108	0	6	0	0
T109	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2019195172	8520	0	0
T1	497112	28	0	0
T2	667392	202	0	0
T3	761076	0	0	0
T4	61240	0	0	0
T5	846216	0	0	0
T6	47296	14	0	0
T10	0	130	0	0
T11	0	105	0	0
T13	0	11	0	0
T17	11440	2	0	0
T18	30412	4	0	0
T19	390620	0	0	0
T20	16788	0	0	0
T107	0	4	0	0
T108	0	10	0	0
T109	0	2	0	0

Assert Coverage for Instance : tb.dut.clkmgr_aes_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	504798793	4066	0	0
TransStop_A	504798793	2072	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798793	4066	0	0
T1	124278	11	0	0
T2	166848	106	0	0
T3	190269	0	0	0
T4	15310	0	0	0
T5	211554	0	0	0
T6	11824	4	0	0
T10	0	60	0	0
T11	0	55	0	0
T13	0	10	0	0
T17	2860	1	0	0
T18	7603	1	0	0
T19	97655	0	0	0
T20	4197	0	0	0
T79	0	1	0	0
T107	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798793	2072	0	0
T1	124278	8	0	0
T2	166848	52	0	0
T3	190269	0	0	0
T4	15310	0	0	0
T5	211554	0	0	0
T6	11824	2	0	0
T10	0	36	0	0
T11	0	24	0	0
T13	0	4	0	0
T17	2860	0	0	0
T18	7603	1	0	0
T19	97655	0	0	0
T20	4197	0	0	0
T107	0	1	0	0
T108	0	2	0	0
T109	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_hmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	504798793	4098	0	0
TransStop_A	504798793	2148	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798793	4098	0	0
T1	124278	14	0	0
T2	166848	110	0	0
T3	190269	0	0	0
T4	15310	0	0	0
T5	211554	0	0	0
T6	11824	11	0	0
T10	0	57	0	0
T11	0	54	0	0
T13	0	9	0	0
T17	2860	0	0	0
T18	7603	1	0	0
T19	97655	0	0	0
T20	4197	0	0	0
T107	0	1	0	0
T108	0	6	0	0
T109	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798793	2148	0	0
T1	124278	7	0	0
T2	166848	49	0	0
T3	190269	0	0	0
T4	15310	0	0	0
T5	211554	0	0	0
T6	11824	4	0	0
T10	0	30	0	0
T11	0	29	0	0
T13	0	3	0	0
T17	2860	0	0	0
T18	7603	1	0	0
T19	97655	0	0	0
T20	4197	0	0	0
T107	0	1	0	0
T108	0	2	0	0
T109	0	1	0	0

Assert Coverage for Instance : tb.dut.clkmgr_kmac_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	504798793	4090	0	0
TransStop_A	504798793	2155	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798793	4090	0	0
T1	124278	16	0	0
T2	166848	105	0	0
T3	190269	0	0	0
T4	15310	0	0	0
T5	211554	0	0	0
T6	11824	12	0	0
T10	0	53	0	0
T11	0	47	0	0
T13	0	9	0	0
T17	2860	1	0	0
T18	7603	1	0	0
T19	97655	0	0	0
T20	4197	0	0	0
T79	0	1	0	0
T107	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798793	2155	0	0
T1	124278	8	0	0
T2	166848	49	0	0
T3	190269	0	0	0
T4	15310	0	0	0
T5	211554	0	0	0
T6	11824	4	0	0
T10	0	33	0	0
T11	0	24	0	0
T13	0	3	0	0
T17	2860	1	0	0
T18	7603	1	0	0
T19	97655	0	0	0
T20	4197	0	0	0
T107	0	1	0	0
T108	0	3	0	0

Assert Coverage for Instance : tb.dut.clkmgr_otbn_trans_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TransStart_A	504798793	4153	0	0
TransStop_A	504798793	2145	0	0

TransStart_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798793	4153	0	0
T1	124278	9	0	0
T2	166848	102	0	0
T3	190269	0	0	0
T4	15310	0	0	0
T5	211554	0	0	0
T6	11824	10	0	0
T10	0	56	0	0
T11	0	54	0	0
T13	0	10	0	0
T17	2860	3	0	0
T18	7603	1	0	0
T19	97655	0	0	0
T20	4197	0	0	0
T79	0	1	0	0
T107	0	1	0	0

TransStop_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	504798793	2145	0	0
T1	124278	5	0	0
T2	166848	52	0	0
T3	190269	0	0	0
T4	15310	0	0	0
T5	211554	0	0	0
T6	11824	4	0	0
T10	0	31	0	0
T11	0	28	0	0
T13	0	1	0	0
T17	2860	1	0	0
T18	7603	1	0	0
T19	97655	0	0	0
T20	4197	0	0	0
T107	0	1	0	0
T108	0	3	0	0