Module Definition
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Module : prim_generic_clock_mux2
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_div2.u_step_down_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T6,T5
01CoveredT1,T6,T5
10CoveredT1,T2,T20 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T6,T5
10CoveredT1,T2,T20
11CoveredT1,T2,T20 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T20
10CoveredT1,T6,T5
11CoveredT1,T6,T5
Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 591798894 591796479 0 0
selKnown1 1421938638 1421936223 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 591798894 591796479 0 0
T1 1318052 1318049 0 0
T2 1974122 1974122 0 0
T3 228148 228145 0 0
T4 8673 8670 0 0
T5 196090 196087 0 0
T6 14020 14017 0 0
T17 3350 3347 0 0
T18 8955 8952 0 0
T19 95450 95447 0 0
T20 4953 4950 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1421938638 1421936223 0 0
T1 316437 316437 0 0
T2 473769 473769 0 0
T3 547956 547953 0 0
T4 44091 44088 0 0
T5 471018 471015 0 0
T6 34050 34047 0 0
T17 8235 8232 0 0
T18 21894 21891 0 0
T19 229398 229395 0 0
T20 12084 12081 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T6,T5
01CoveredT1,T6,T5
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T6,T5
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T6,T5
11CoveredT1,T6,T5
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 237252428 237251623 0 0
selKnown1 473979546 473978741 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 237252428 237251623 0 0
T1 527319 527318 0 0
T2 789853 789853 0 0
T3 91259 91258 0 0
T4 3469 3468 0 0
T5 78436 78435 0 0
T6 5608 5607 0 0
T17 1340 1339 0 0
T18 3582 3581 0 0
T19 38180 38179 0 0
T20 1990 1989 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 473979546 473978741 0 0
T1 105479 105479 0 0
T2 157923 157923 0 0
T3 182652 182651 0 0
T4 14697 14696 0 0
T5 157006 157005 0 0
T6 11350 11349 0 0
T17 2745 2744 0 0
T18 7298 7297 0 0
T19 76466 76465 0 0
T20 4028 4027 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T6,T5
01CoveredT1,T6,T5
10CoveredT1,T2,T20 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T6,T5
10CoveredT1,T2,T20
11CoveredT1,T2,T20 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT1,T2,T20
10CoveredT1,T6,T5
11CoveredT1,T6,T5
Assert Coverage for Instance : tb.dut.u_no_scan_io_div2_div.gen_generic.u_impl_generic.gen_div2.u_step_down_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 235920894 235920089 0 0
selKnown1 473979546 473978741 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 235920894 235920089 0 0
T1 527075 527074 0 0
T2 789344 789344 0 0
T3 91259 91258 0 0
T4 3469 3468 0 0
T5 78436 78435 0 0
T6 5608 5607 0 0
T17 1340 1339 0 0
T18 3582 3581 0 0
T19 38180 38179 0 0
T20 1968 1967 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 473979546 473978741 0 0
T1 105479 105479 0 0
T2 157923 157923 0 0
T3 182652 182651 0 0
T4 14697 14696 0 0
T5 157006 157005 0 0
T6 11350 11349 0 0
T17 2745 2744 0 0
T18 7298 7297 0 0
T19 76466 76465 0 0
T20 4028 4027 0 0

Line Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1

Cond Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions55100.00
Logical55100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T6,T5
01CoveredT1,T6,T5
10Unreachable 

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T6,T5
10Unreachable
11Unreachable 

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Unreachable
10CoveredT1,T6,T5
11CoveredT1,T6,T5
Assert Coverage for Instance : tb.dut.u_no_scan_io_div4_div.gen_generic.u_impl_generic.u_clk_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 118625572 118624767 0 0
selKnown1 473979546 473978741 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 118625572 118624767 0 0
T1 263658 263657 0 0
T2 394925 394925 0 0
T3 45630 45629 0 0
T4 1735 1734 0 0
T5 39218 39217 0 0
T6 2804 2803 0 0
T17 670 669 0 0
T18 1791 1790 0 0
T19 19090 19089 0 0
T20 995 994 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 473979546 473978741 0 0
T1 105479 105479 0 0
T2 157923 157923 0 0
T3 182652 182651 0 0
T4 14697 14696 0 0
T5 157006 157005 0 0
T6 11350 11349 0 0
T17 2745 2744 0 0
T18 7298 7297 0 0
T19 76466 76465 0 0
T20 4028 4027 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%